% -*- Mode:Text -*- 

\chapter{Pins and signals}\label{sect.c-pins}

 \newcommand{\pin}[3]{\tt#1&\sym#2&\sym#3\\}
\newenvironment{pinout}[2]{
    $$
    \begin{tabular}{|c|ll|}
	\multicolumn{3}{c}{#2 (#1 pins)}\\
 	\hline type & \multicolumn{2}{|c|}{name}\\\hline\hline}%
{\hline\end{tabular}
    $$}

\section{Pin types}

The \cam\ chip is packaged in a 68-pin PLCC.

The pins are sorted into functional groups, each of which is discussed
in a separate subsection. In the pinout table in each subsection, the
table header gives the total number of pins in the group and a
descriptive name for the group itself (\dram\ interface, \tbus\
interface, etc.). For each pin, the tables give the pin number, its
type, according to table (\eq{pin-types}), and then the pin's
mnemonics followed by its full name.

 \def\In{{\tt I}}
 \def\Out{{\tt O}}
 \def\TS{{\tt T}}
 \def\IO{{\tt B}}
 \def\Wor{{\tt W}}
  
 \begin{equation}\label{eq.pin-types}
 \begin{tabular}{|c|p{2.0in}|}\hline 
 Type & \multicolumn{1}{c|}{Description} \\\hline\hline
 \In & {\em Input}.\quad This pin is sensed as an input.\\\hline
 \Out & {\em Output}.\quad This pin has an output driver, which is always
enabled.\\\hline
 \TS & {\em Tri-state}.\quad This pin has an output driver which can
be disabled.\\\hline
 \IO & {\em Bidirectional}.\quad This pin is sensed as an input, and is
driven as a tri-state output.\\\hline
 \Wor & {\em Wire-{\sc or}}.\quad This pin is driven in a way suitable for
wire-{\sc or}ing (implementation details to be decided).\\\hline
 \end{tabular}
 \end{equation}



\section{DRAM interface}\label{sect.dram-side-pins}

 \begin{pinout}{19}{\Dram\ interface}
 \pin{\Out}{DA(10:0)}{DRAM Address(10:0)}
 \pin{\IO}{DD(3:0)}{DRAM Data(3:0)}
 \pin{\Out}{DRAS*}{DRAM Row Address Strobe*}
 \pin{\Out}{DCAS*}{DRAM Column Address Strobe*}
 \pin{\Out}{DWT*}{DRAM Write Enable*}
 \pin{\Out}{DOE*}{DRAM Output Enable*}
 \end{pinout}

These are the address, data, and control signals for the \dram\ chip
associated with each \chip. 

\medskip

Since we use nybble-wide chips, total \dram\ capacity with 11 address
lines ({\sym DA(10:0)}) is $4\cdot2^{2\cdot 11}$, or 16 Mbits.

Once we are in fast-page or static-column mode, typically a \dram\
read/write operation takes 4 clock cycles; in the first two, a nybble
is read, in the second, a nybble is written.

\section{SRAM interface}\label{sect.sram-side-pins}

 \begin{pinout}{4}{\Sram\ interface}
 \pin{\Out}{SA0}{SRAM Address, Bank 0}
 \pin{\Out}{SA1}{SRAM Address, Bank 1}
 \pin{\IO}{SD0}{SRAM Data, Bank 0}
 \pin{\IO}{SD1}{SRAM Data, Bank 1}
 \end{pinout}

These are the address and data signals for the two \sram\ lookup
tables, \lut0 and \lut1.  The \sram\ control signals are distributed
on a module-wide basis by means of four of the {\sym Multipurpose}
pins (\sect{MPCR}).

\section{Glue}\label{sect.glue-pins}

 \begin{pinout}{6}{Glue}
 \pin{\IO}{XM}{X-Minus}
 \pin{\IO}{XP}{X-Plus}
 \pin{\IO}{YM}{Y-Minus}
 \pin{\IO}{YP}{Y-Plus}
 \pin{\IO}{ZM}{Z-Minus}
 \pin{\IO}{ZP}{Z-Plus}
 \end{pinout}

These are the signals that allow one to ``glue'' modules edge-to-edge
so as to achieve an array of indefinite extent.

\section{Flywheel bus}\label{sect.flywheel-pins}

 \begin{pinout}{3}{Flywheel bus}
 \pin{\Out}{FDO}{Flywheel Data Output}
 \pin{\In}{FIE*}{Flywheel Input Enable*}
 \pin{\In}{FDI}{Flywheel Data Input}
 \end{pinout}

At every step, the entire \dram\ contents (or whatever fraction of it
is actually used for the model's state variables) is serially made
visible to the outside world via the {\sym Flywheel Data Output} pin,
before being sent to the lookup table.  External circuitry can use
these data for analysis purposes; and can replace any of
these data bits with externally supplied ones. On every
clock cycle in which {\sym Flywheel Input
Enable*} is asserted, the internal data bit is replaced
with one that is externally supplied via the {\sym Flywheel Data Input}
pin. The timing of this injection---either one or four clock cycles\footnote
	{Depending on the setting of the {\sym FPL} bit in the
{\sym Hardware Environment Register} (\sect{HER}).}\relax
	---later than when the original bit appeared on the {\sym FDO}
pin, allows for the original bit to be taken into consideration
when generating the replacement bit.

\section{\tbus\ interface}\label{sect.tbus-interface}

 \begin{pinout}{8}{\tbus}
 \pin{\In}{TF*}{\tbus\ Frame*}
 \pin{\In}{TOS}{\tbus\ Outbound Tag}
 \pin{\Out}{TIS}{\tbus\ Inbound Tag}
 \pin{\IO}{TD}{\tbus\ Data}
 \pin{\Out}{TFT*}{\tbus\ Frame Through*}
 \pin{\Out}{TOST}{\tbus\ Outbound Tag Through}
 \pin{\In}{TIST}{\tbus\ Inbound Tag Through}
 \pin{\IO}{TDT}{\tbus\ Data Through}
 \end{pinout}

The above \tbus\ signals are directly handled by the \chip.
Other \tbus\ related signals go through significant on-board conditioning,
and are listed in \sect{misc-pins}.

\section{Miscellaneous}\label{sect.misc-pins}

 \begin{pinout}{9}{Miscellaneous}
 \pin{\In}{Reset*}{Reset*}
 \pin{\In}{Sync*}{Sync*}
 \pin{\In}{Clock}{Clock}
 \pin{\Out}{MP}{Multipurpose}
 \pin{\Wor}{Int*}{Interrupt*}
 \pin{\Wor}{ModSel}{Module Select}
 \pin{\TS}{VO}{Video Out}
 \end{pinout}


The {\sym Interrupt*} pins from the 16 chips of a module are wire-{\sc
or}ed together. The resulting signal is merged with {\sym
Scan-in-Progress} information and output on one of the 16 {\sym
Multipurpose} pins (\sect{MPCR}), to be used, after proper
conditioning, as the \tbus\ {\sym Status*} signal contributed by the module.

The {\sym Module Select} pins from the 16 chips of a module are
wire-{\sc and}ed together, to allow the individual chips to contribute
to a module-wide {\sc and} and sense its result, as explained in
\sect{modselect}. As each pin will be actively driven immediately
before the clock cycle in which the {\sc and} operation will be
performed, the pull-up resistor connected to this wire is only for
long-term bleeding purposes,

{\sym Reset*}, {\sym Sync*}, and {\sym Clock} are derived from the
corresponding \tbus\ signals; the latter are fanned out to the
tree branches by on-board circuitry, without involving the \chip.

\section{Spares, reserved}

 \begin{pinout}{2}{Reserved}
 \pin{\In}{Esc0}{Escape0}
 \pin{\In}{Esc1}{Escape1}
 \end{pinout}

The behavior of the \chip\ is characterized only when the two pins
{\sym Escape0} and {\sym Escape1} are tied to logical 0.

In some versions of the die used for the \chip, for fabrication
convenience some of the spare die area may have been used for other chips.
A scheme presently being considered for this multiplexing of
functions on the same die is the following
 \begin{equation}\label{eq.chip-mode}
 \begin{tabular}{|cc|p{1.25in}|}\hline
	\sym Esc0 & \sym Esc1 & \multicolumn{1}{c|}{chip selected}\\\hline\hline
	0 & 0 & \chip\\
	0 & 1 & {\sc ctlsv} chip\\
	1 & 0 & {\sc fsm} chip\\
	1 & 1 & {\sc dataregs} chip\\\hline
 \end{tabular}\;.
 \end{equation}
	The \cam\ controller will use one {\sc fsm}, two {\sc stlsv},
and two {\sc dataregs} chips.

\section{Power, ground}

\endinput




\addtocounter{footnote}{-1}\footnotetext
	{Since we use nybble-wide chips, total \dram\ capacity with 11
address lines is $2^{2\cdot 11}\cdot 4$, or 16M bits.}
\addtocounter{footnote}{1}\footnotetext
	{Once we are in fast-page or static-column mode, typically a
\dram\ read/write operation takes 4 clock cycles; in the first two, a
nybble is read, in the second, a nybble is written.}
