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\chapter{Registers}\label{sect.regs}

This chapter systematically presents the registers that make up the
\chip\ {\em register address space}---which is directly accessible by
the \bus\ (\cf{chip-regs}). Other on-chip data structures are
accessed only in an indirect way (for instance, the {\sym Event
Counter} is read by the user via a register called the {\sym Event
Count Register}), or are of no immediate relevance to the \cam\
user.

Each register is presented in a separate section; the section number
itself (e.g., the `\ref{sample-section}' in \sect{MIDR})
coincides with the register's address (\sect{chip-regs}). The makeup
of each register is summarized in tabular form immediately below the
section title. The register's length in bits is given, followed by the
register's mnemonic and its full name.  Often, a register is actually
a collection of logically separate components; in such cases the
components themselves are individually listed, starting from the one
at the least-significant-digit end of the register. For example, the
30 bits of the {\sym Kick Register} (\sect{KR}) comprise a
24-bit {\sym Kick Amount} (whose least significant bit is the
least significant bit of the entire {\sym Kick Register}), three
one-bit {\sym Kick Sign}s, and three one-bit {\sym Kick Max Flag}s.
This listing order corresponds to the order in which bits are
transmitted to or received from a register, i.e., least-significant
bit first.

All registers are both readable and writable, although most would only
be read for error recovery or test purposes.  At power-on reset, all
registers except the {\sym Module ID Register} are cleared to zero
(see \sect{MIDR}); a host-initiated, {\em soft}, reset is similar, but
leaves the DRAM contents and several registers ({\sym OSR}, {\sym IR}
and {\sym DOCR}) unchanged.

As mentioned in \sect{chip-regs}, the two I/O registers, namely the
{\sym Scan I/O Register} and the {\sym LUT I/O Register}, follow their
own conventions concerning length of transfers.  Moreover, the {\sym
Event Count Register}, whose full length is 25 bits, may be
read or written for only part of its length, as specified by the {\sym
Event Counter Length} component of the {\sym Scan Format Register}.

\medskip

For reference, a summary description of \cam\ registers is given
immediately below---detailed descriptions follow.



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\setcounter{section}{-1}
\section{Module Select Register}\label{sect.SR}

 \begin{register}{\ \ 3}{MSR}{Module Select Register}
 \end{register}
	 In order for a \cam\ module to be enabled to accept the data
broadcast by the host on the \bus\ during a write frame or put its own
data on the \bus\ during a read frame, the module must be {\em
selected}, as explained in \sect{modselect}. The parameters upon which
this selection depends are specified by a three-bit {\em selection
code} written to the {\sym Module Select Register}.  Selection codes
specify an internal register and a target value to be matched (see
table \eq{selection-codes.rpt}): a module will be selected when all
\cam\ chips in the module simultaneously indicate a selection match.

 \begin{equation}\label{eq.selection-codes.rpt}
 \begin{tabular}{|c|l|l|}\hline
	\small selection code   & \multicolumn{2}{c|}{bits to be matched}\\
	(\sym MSR) & internal & target\\\hline\hline
	000 & \sym MIDR & 0 \\
	010 & \sym MIDR & 1 \\
	100 & \sym MIDR & \sym LIR \\
	110 & \sym Glue-AND & 0 \\\hline
	001 & \sym GIDR & 0 \\
	011 & \sym GIDR & 1 \\
	101 & \sym GIDR & \sym LIR \\
	111 & \multicolumn{2}{c|}{don't care} \\\hline
 \end{tabular}\
 \end{equation}

Owing to its special role in the selection mechanism, the {\sym Module
Select Register} ``escapes selection,'' in the sense that data {\em
written} to it by the \bus\ are accepted by {\em every} module
regardless of the module's current selection status.  The selection
status of a module (i.e., selected or not) is latched when this
register is written, and remains in force until this register is
written again.

The {\sym Module Select Register} also escapes normal selection on
reads: read operations require a single module to be selected, and so
the normal selection mechanism wouldn't allow us to read back the
current selection status of \cam\ if more than one module happens to
be currently selected!  Since the {\sym Module Select Register}s of
all modules are always written simultaneously, it doesn't matter {\em
which} module responds to a read of the {\sym MSR}, as long as only
one does: a bit in the {\sym Hardware Environment Register}
(\sect{HER}) is used to single out one particular module for this
``honor''.


\section{Run Mode Register}\label{sect.RMR}

\begin{register}{\ \ 5}{RMR}{Run Mode Register}
	\compositeof
	\subreg{2}{SSM}{Scan Sync Mode}
	\subreg{1}{ECT}{Event Count Transfer}
	\subreg{1}{RPK}{Repeat Previous Kick}
	\subreg{1}{ALT}{Active LUT Toggle}
 \end{register}
	Writing a nonzero value to the {\sym Scan Sync Mode}
{\em schedules} a scan (\cf{}), i.e., instructs the \chip\ to start a
new scan as soon as possible; the specific value written in the
register determines to what extent scans and sweeps must be
synchronized to the {\sym VCAM} and {\sym HCAM} signals---as detailed
in table \eq{scan-sync-mode}. At the end of the scan, the register is
automatically cleared.

 \begin{equation}\label{eq.scan-sync-mode}
 \begin{tabular}{|c|p{2.25in}|}\hline
	\sym SSM & \multicolumn{1}{c|}{Scan Sync Mode}\\\hline
	0 & \parhead{Standby} No scan scheduled. \\
	1 & \parhead{Frame sync} The starting of individual sweeps of
the scan will wait for {\sym HCAM}; the first sweep (and thus the
entire scan) will wait for {\sym VCAM} (which also coincides with an
{\sym HCAM}).  \\
	2 & \parhead{Line sync} Individual sweeps of the scan will
wait for {\sym HCAM}.\\
	3 & \parhead{Free run} The scan will start immediately,
and sweeps will follow one another without any gaps.\\\hline
 \end{tabular}
 \end{equation}
	{\sym HCAM} and {\sym VCAM} are synchronized with the signals
{\sym HMON} and {\sym VMON} that are sent to the {\sc crt} monitor
to which Display Data are fed (\sect{DSR}). Thus, in a scan of sync
mode 1 a sector is scanned in lockstep with the scanning of the {\sc
crt} monitor.
	A sync mode 2 scan typically consists of a single sweep; this is
used when one intends to change some of the registers (e.g., the {\sym
Kick Register}) from one sweep to the next.
	A sync mode 3 scan, in which the timing of the scanning is not
constrained by real-time display considerations, yields, of course,
the fastest scanning rate.

\medskip

In all cases, the actual start of each sweep is shifted in time by the
amount specified by the {\sym Tree Balancing Delay} (\sect{HER}), to
insure that modules placed at different distances from the \bus\ root
will all scan in lockstep (\cf{tree-balancing}).

\medskip

The {\sym Scan-in-Progress} signal is defined as the logical {\sc or}
of the two bits of the {\sym Run Mode Register}, and has a value of 1
from the moment a scan is scheduled to the moment the scan itself
ends. This signal is made available to the \cam\ interface via the
{\sym Status} line (\cf{SFR}, \andsect{}), to allow the interface to
determine when a scan is finished, and thus when operations that must
wait for end-of-scan can proceed (e.g., the scheduling of a new
scan).

\medskip

Although the {\sym Run Mode Register} isn't double buffered, the delay
between the end of one scan and the beginning of the next need not be
longer than a few cycles. In fact, the data to be sent to this
register to schedule a new scan can be loaded into the \cam\
interface during the current scan, ready to be broadcast to the \cam\
modules as soon as the {\sym Scan-in-Progress} signal is no longer
asserted (\cf{cam-wait}). (As explained in \sect{ECR}, the event
counts for the current scan are double-buffered and can be read at
leisure {\em after} the new scan has started.)

\medskip

Several other actions associated with scheduling a scan are controlled
by the {\sym Run Mode Register}, and occur (if indicated) when this
register is written.

The {\sym Event Count Transfer} bit controls whether to copy the value
in the {\sym Event Counter} (accumulated during previous scans) into the
{\sym Event Count Register}, and to then clear the {\sym Event Counter}
itself.  Thus before starting a new scan, the count from the previous
scan can be made available to be read back by the host during the new
scan (\sect{ECR}).

The {\sym Repeat Previous Kick} bit controls whether to add the {\sym
Kick Amount} to the {\sym Offset Register}.  Since the kick is always
added whenever the {\sym Kick Register} is written, it is only
necessary to do this here when scheduling a scan that repeats the same
kick as that specified for the previous scan.

The {\sym Active LUT Toggle} switches the roles of {\em active} and
{\em inactive} \lut\ between \lut\ 0 and \lut\ 1.  The active \lut\ is
the one that will be used as the main processing element in the data
stream (cf.\ \fig{style-block}).  The other, or inactive, \lut\ is
accessible to the \bus\ via the {\sym LUT I/O Register} (\cf{LIR});
specifically, it can be loaded with new contents even while a scan is
in progress (\cf{bus-usage}).

One can find out which of the two \lut{}s is the active one by reading
the {\sym Active LUT Select} bit in the {\sym Hardware Environment
Register} (\sect{HER}). By writing that bit, one can force a specific
\lut\ (rather than just ``the other one'') to be the active one.


\section{Kick Register}\label{sect.KR}

 \begin{register}{\ 30}{KR}{Kick Register}
	\compositeof
	\subreg{24}{KA}{Kick Amount}
	\subreg{1}{XKS}{X-Kick Sign}
	\subreg{1}{YKS}{Y-Kick Sign}
	\subreg{1}{ZKS}{Z-Kick Sign}
	\subreg{1}{XKMF}{X-Kick Max Flag}
	\subreg{1}{YKMF}{Y-Kick Max Flag}
	\subreg{1}{ZKMF}{Z-Kick Max Flag}
 \end{register}
	 The {\sym Kick Register}s on the different \chip{}s in each
\cam\ module determine how data streams from the corresponding layers
will be recombined during the next scan to form the ``bit piles'' that
are passed through the active \lut\ for updating (\cf{sites-layers}
and \chapt{scanning}).  In particular, this register specifies how the
data contained in the multidimensional ``layer'' controlled by a given
\chip\ should be shifted relative to other such layers.

The bits of the {\sym Kick Amount} constitute a $d$-component vector,
$\vec{k}$, representing a displacement in a $d$-dimensional space.
The structure of this vector (number $d$ of components and number of
bits devoted to each component) is determined by the {\sym Dimension
Register}, as explained in \sect{}. Just before the beginning of a
scan this vector is subtracted from the origin of coordinates (another
vector with the same structure which is kept in the {\sym Offset
Register}; \sect{OR}).  In the scanning and gluing context of \cam,
subtracting $k$ from the origin of a layer is equivalent to shifting
the layer's data by $\vec{k}$. We call this virtual-shift mechanism a
`kick'.

\medskip

More specifically, the {\sym Dimension Cut Mask} in the {\sym
Dimension Register} determines how the entire site-address arithmetic
chain is subdivided into separate slices each corresponding to one
dimension.  Each slice of the {\sym Kick Amount} specifies the size of
the kick for the corresponding dimension (\sect{}). For the three
extendible dimensions $x$, $y$, and $z$ this amount is further
qualified by a {\sym Kick Sign} and a {\sym Kick Max Flag}.

Basically, the kick component for each of the dimensions is encoded in
two's complement notation. Suppose that in a given dimension the
address slice is eight bits wide, so that the {\sym Kick Amount}
component for that dimension ranges from {\tt 00} to {\tt FF} (in
hex). A kick of {\tt 01} will circularly shift (within the sector
boundaries) the layer's data by one position in the positive
direction; a kick of {\tt FF} will shift the data by 255 positions in
the positive direction, or, which is equivalent, by one position in
the negative direction.

For each of the three extendible dimensions, the shift specified by
the {\sym Kick Amount} affects the layer as a whole (rather than each
sector being independently circularly shifted), and the {\sym Kick
Sign} is used as the most significant bit in the two's complement
notation.  Still assuming an eight-bit slice as above, one would
obtain in this way a kick range from $-256$ to +255; the value +256 is
also possible using only data from nearest neighboring modules, and is
indicated by setting the corresponding {\sym Kick Max Flag}.  The
entire range of cases, for an eight-bit slice, is summarized by the
following table (using the $x$ dimension for definiteness)
 \begin{equation}\label{eq.kick-range}
 \begin{tabular}{|c|c|c|r|}\hline
	\sym XKMF & \sym XKS & \sym KA &\\
	Max flag & sign & amount & \multicolumn{1}{c|}{Actual
shift}\\\hline
	1 & 0 & \tt 00 & +256\\
	0 & 0 & \tt FF & +255\\
	0 & 0 & \tt FE & +254\\
	$\vdots$ & $\vdots$ & $\vdots$ & $\vdots$ \\
	0 & 0 & \tt 02 & +2\\
	0 & 0 & \tt 01 & +1\\
	0 & 0 & \tt 00 & 0\\
	0 & 1 & \tt FF & -1\\
	0 & 1 & \tt FE & -2\\
	$\vdots$ & $\vdots$ & $\vdots$ & $\vdots$ \\
	0 & 1 & \tt 02 & -254\\
	0 & 1 & \tt 01 & -255\\
	0 & 1 & \tt 00 & -256\\\hline
 \end{tabular}
 \end{equation}

Note that if the {\sym Kick Sign} and {\sym Kick Max Flag}s are both
fixed at zero, and the {\sym Dimension Cut Pointer}s (\sect{DR}) are
set appropriately (a value of 31), then $x$, $y$, and $z$ can be used
as internal dimensions---they will be internally wrapped around and no
use will be made of glue.


\section*{Sources and Destinations}

Central to the \cam\ updating and analysis process are five internal
inputs within each \chip\ which we shall call {\em destinations}:
 \begin{itemize}
	\item {\em LUT Address} (\sect{LASR}). The \lut\ Address bit
contributed by the \chip.  Collectively, the sixteen \lut\ Address
bits contributed by a \chip\ set make up the address used, at every
site of a scan, for lookup in the active \lut.
	\item {\em Flywheel Output} (\sect{FOSR}). The bit to be
placed on the \chip's {\sym Flywheel Data Output} pin
(\sect{flywheel-pins})---perhaps to be modified and returned through
the {\sym Flywheel Data Input} pin.
	\item {\em Site Data} (\sect{SDSR}). The Site Data bit
contributed by the \chip.  Collectively, the sixteen Site Data bits
contributed by a \chip\ set make up the new value to be written in the
site being scanned (cf.\ \fig{site-layer}).
	\item {\em Event Counter} (\sect{ECSR}). The bit to be fed to
the \chip's {\sym Event Counter} (see \sect{event-counter}). Each of
the sixteen \chip{}s of a module has a separate event counter.
	\item {\em Display Data} (\sect{DSR}) The data to be displayed
on the dedicated monitor, or read back by the host during scan-io
(\sect{SIOR}).
 \end{itemize} These inputs can be fed, under software control, with
data derived from a number of sources.  Separate registers (described
in the next few sections) control the data source that is attached to
each of these destinations.  In all cases, source selection and
combination is made in two stages, using a two-bit {\em select}
register and a four-bit {\em map} register.  The select register
selects one source out of four, namely,
 \begin{enumerate}
\setcounter{enumi}{-1}
	\item The Unglued Data bit.
	\item The incoming \bus\ Data bit (\sect{SIR},
\andsect{SIR}).
	\item The Flywheel Input bit.
	\item \begin{enumerate} \item {\it When the destination is
either the \lut\ Address bit or the Flywheel Output bit:} one bit of
the {\sym Site Address}, as specified by the {\sym Site Address Bit
Select Register}. \item {\it For all other destinations:} the \lut\
output.  \end{enumerate}
 \end{enumerate}
	The map register specifies how the selected source bit is to
be logically combined with another source, namely, the Glued Data bit.
The two sources are used as a two-bit index (Glued Data bit is LSB) to
choose one of the four bits of the map register (the LSB of the map
register has index 0).  Thus the four bits of this register identify
one of the sixteen possible Boolean functions of two Boolean inputs;
the two source bits provide the inputs to this function; the output
represents the value that is actually sent to the destination.

For each of the fifteen possible values of the map register, the table
below gives the logical meaning of the resulting bit sent to the
destination. The selected source bit is abbreviated $sel\_src$ below,
{\em glue} indicates the Glued Data bit.
 \begin{equation}\label{eq.mappings}
 \begin{tabular}{|c|p{1.75in}|}\hline
	{\rm Map} & \multicolumn{1}{c|}{Destination Input gets ...}\\\hline
	0 & 0, ignores both sources \\
	1 & glue NOR sel\_src\\
	2 & glue AND (NOT sel\_src)\\
	3 & NOT sel\_src \\
	4 & (NOT glue) AND sel\_src\\
	5 & NOT glue \\
	6 & glue XOR sel\_src \\
	7 & glue NAND sel\_src\\
	8 & glue AND sel\_src\\
	9 & glue EQUALS sel\_src\\
	10 & glue \\
	11 & glue OR (NOT sel\_src)\\
	12 & sel\_src \\
	13 & sel\_src OR (NOT glue)\\
	14 & glue OR sel\_src\\
	15 & 1, ignores both sources\\\hline
 \end{tabular}
 \end{equation}


\section{Site Address Bit Select Register}\label{sect.SABSR}

 \begin{register}{\ \ 5}{SABSR}{Site Address Bit Select Register}
 \end{register}

This register selects one of the {\sym Site Address}'s 24 bits, to be
made available as the fourth choice for the select portion of the
data-combining logic controlled by the {\sym LUT Address Source
Register} and the {\sym Flywheel Output Source Register}.


\section{LUT Address Source Register}\label{sect.LASR}

 \begin{register}{\ \ 6}{LASR}{LUT Address Source Register}
	\compositeof
	\subreg{2}{LAS}{LUT Address Select}
	\subreg{4}{LAM}{LUT Address Map}
 \end{register}

{\sym LUT Address Select} and {\sym LUT Address Map} are used to
construct the source for the LUT Address destination
signal (as discussed above).


\section{Flywheel Output Source Register}\label{sect.FOSR}

 \begin{register}{\ \ 6}{FOSR}{Flywheel Output Source Register}
	\compositeof
	\subreg{2}{FOS}{Flywheel Output Select}
	\subreg{4}{FOM}{Flywheel Output Map}
 \end{register}

{\sym Flywheel Output Select} and {\sym Flywheel Output Map} are
used to construct the source for the Flywheel Output
destination signal (as discussed above).


\section{Site Data Source Register}\label{sect.SDSR}

 \begin{register}{\ \ 6}{SDSR}{Site Data Source Register}
	\compositeof
	\subreg{2}{SDS}{Site Data Select}
	\subreg{4}{SDM}{Site Data Map}
 \end{register}

{\sym Site Data Select} and {\sym Site Data Map} are
used to construct the source
for the Site Data destination signal (as discussed above).


\section{Event Counter Source Register}\label{sect.ECSR}

 \begin{register}{\ \ 6}{ECSR}{Event Counter Source Register}
	\compositeof
	\subreg{2}{ECS}{Event Counter Select}
	\subreg{4}{ECM}{Event Counter Map}
 \end{register}

{\sym Event Counter Select} and {\sym Event Counter Map} are
used to construct the source
for the Event Counter destination signal (as discussed above).


\section{Display Source Register}\label{sect.DSR}

 \begin{register}{\ \ 7}{DSR}{Display Source Register}
	\compositeof
	\subreg{2}{DDS}{Display Data Select}
	\subreg{4}{DDM}{Display Data Map}
	\subreg{1}{DE}{Display Enable}
 \end{register}
	The {\sym Display Source Register} controls the relationship
of the \cam\ unit to a dedicated video display, and also controls
which data is read back during a scan-io operation (\cf{SIOR}).
    
\medskip

The {\sym Display Enable} indicates whether or not the \chip\
should enable its (tri-state) {\sym Video Out} pin (\sect{misc-pins}),
thus putting the Display Data signal onto the video output bus
(\cf{}).

The {\sym Display Data Select} and the {\sym Display Data Map} are
used to construct the source for the Display Data destination signal
(as discussed above).

Note: A Display Data signal that is enabled onto the video output bus
outputs a value of zero during any clock when there is no valid
display bit available.


\section{Show Scan Register}\label{sect.SSR}

\begin{register}{\ \ 1}{SSR}{Show Scan Register}
 \end{register}

The \cam\ interface must wait for an end-of-scan condition before it
proceeds to read or write a register involved in the scan.  Since it
is possible that not all modules are performing identical scans (e.g.,
one distinguished module may be acting as a frame buffer), we
explicitly choose which module is to provide feedback on the state of
the scan.  Note that, on the selected module, this information is
normally combined with the {\sym Interrupt} signal coming back from
\cam\ to produce the {\sym Status} signal.  Note also that this signal
is only needed at most once per module, and so is provided as an
output from a {\sym Multipurpose Pin} (\cf{MPCR}).

More specifically, when {\sym Show Scan} is set, the {\sym
Scan-in-Progress} signal generated by the \chip\ (\sect{RMR}) is
multiplexed onto the \bus\ {\sym Status} line, which also carries the
\bus\ {\sym Interrupt*} signal: the {\sym Scan-in-Progress} signal is
chopped ({\sc and}ed with a signal that toggles at the clock rate),
inverted, and {\sc and}ed with {\sym \bus\ Interrupt*}.


\section{Event Count Register}\label{sect.ECR}

 \begin{register}{-{}-{}-}{ECR}{Event Count Register}
 \end{register}
	The {\sym Event Count Register} is used as a buffer for the
\chip's event counter (\sect{event-counter}), to permit reading the
count from the previous scan even as a new count is accumulating
during the current scan.  It has the same physical length of 25 bits
as the event counter, and is loaded with the contents of the latter at
the moment that the {\sym Run Mode Register}'s {\sym Event Count
Transfer} bit is set.

\medskip

The event count is the most likely quantity that will be read from all
modules at possibly frequent intervals during a simulation.  Two
provisions are made to optimize this readback.

With short scans, new event counts will be available with
great frequency;\footnote
	{In fact, short scans are usually set up in order to
measure totals or averages separately over small patches of space
rather than over the entire space encompassed by a module.}
	on the other hand, in this situation the maximum possible
value recorded by the event counter will be small, so that the
effectively used length of this counter may reduce to just a few bits.
The {\sym Event Counter Length} (\sect{SFR}) specifies
this effective length, instructing the \chip\ to transmit only that
many bits during the read-out of the {\sym Event Count Register}.
Note that when less than 25 bits are read from this register, the
contents of the register are circularly shifted, and so the same value
cannot be simply reread.

By making use of the sequential-read mode (\sect{sequential-read}),
it is possible to read all event counters in a single \bus\ frame,
with automatic switchover of bus control from one module to the next.
This allows all event counters to be read without repeatedly changing
bus direction to explicitly select each module in turn.


\section{LUT Index Register}\label{sect.LIR}

 \begin{register}{\ 16}{LIR}{LUT Index Register}
 \end{register}
	The {\sym LUT Index Register} indicates which entry of the
inactive \lut\ (\sect{RMR}) is to be accessed. The pointer
autoincrements each time an entry is read or written, thus pointing to
the next entry to be accessed.

The same register does double duty in a different context.  When event
counters are read back in sequential-read mode (\sect{ECR},
\andsect{sequential-read}), the {\sym LUT Index Register} provides the
target name specifying which module is to be selected in turn.  The
pointer autoincrements each time {\sym Event Count Length} number of
bits have been read, thus pointing to the next module to be selected.

In principle, each \chip\ is responsible only for one bit of the
pointer. Unfortunately, in order to gang the single bits from
individual \chip{}s into a 16-bit, module-wide autoincrementing
counter one would need to propagate a ripple carry across many chips.
Since ripple propagation from chip to chip would be too slow for our
purposes, the entire counter is repeated within each \chip\ (ripple
propagation within a single chip is an order of magnitude faster), and
each chip of a set is instructed by its {\sym LUT Index Permutation
Register} (\sect{LIPR}) to use a different bit of this counter.


\section{LUT Index Permutation Register}\label{sect.LIPR}

 \begin{register}{\ \ 5}{LIPR}{LUT Index Permutation Register}
 \end{register}
	As mentioned in \sect{LIR}, each \chip\ has its own copy of
the entire {\sym LUT Index Register} but uses only one bit of it. The
{\sym LUT Index Permutation Register} specifies which of the {\sym LUT
Index Register}'s 16 bits is to be used by a given \chip.

Normally, \chip\ 0 will use the bit in position 0, \chip\ 1 that in
position 1, etc.  However, it is possible to specify a different
correspondence between \chip{} numbers and bit positions; this feature
can be used, during \lut\ downloading, to interchange the roles of
different inputs to the \lut.  One can also bypass the {\sym LUT Index
Register} and send instead a constant of 0 or 1.

The available choices are summarized in the following table
 \begin{equation}\label{eq.lppr-choices}
 \begin{tabular}{|l|l|}\hline
	{\sym LIPR} & \multicolumn{1}{|c|}{\sym \lut\ address bit source}\\\hline\hline
	$\phantom{0}$0 & bit $\phantom{0}$0 of {\sym LUT Index Register}\\
	$\phantom{0}$1 & bit $\phantom{0}$1 of {\sym LUT Index Register}\\
	$\phantom{0}$2 & bit $\phantom{0}$2 of {\sym LUT Index Register}\\
	$\phantom{0}$$\vdots$\ & \quad$\vdots$\\
	15 & bit 15 of {\sym LUT Index Register}\\ \hline
	16--29 & not used\\\hline
	30 & 0\\
	31 & 1\\\hline
 \end{tabular}\
 \end{equation}

  
\section{LUT I/O Register}\label{sect.LIOR}

 \begin{register}{-{}-{}-}{LIOR}{LUT I/O Register}
 \end{register}
	\noindent As mentioned in \sect{chip-regs}, the {\sym LUT I/O
Register} is used for writing data to the inactive \lut\
(\sect{RMR}) or reading data from it, and does not have an
intrinsic length.

The data transfer starts from the location initially specified by the
{\sym LUT Index Register} (\sect{LIR}), which will have been set up
previously, and continues upwards (this pointer is autoincrementing).
The transfer ends when the {\sym LUT Index Register} reaches its
terminal count; whereupon, on a read frame the \chip\ quits sending
bits, while on a write frame it signals an error by setting the {\sym
Register Length Interrupt Flag} (\cf{IR}) if addtional bits are
received .  After an error-free transfer the {\sym LUT Index Register}
contains a value of zero.

\medskip

If the {\sym Verify Write Flag} (\sect{VWR}) is set, any portion of
the inactive \lut\ may of course be checked instead of written.  Note
that, unlike all other registers, it is not possible to use the verify
write mode to perform {\em write-per-bit} (see \sect{VWR}) to the {\sym LUT
I/O Register}.


\section{Scan Index Register}\label{sect.SIR}

 \begin{register}{\ 24}{SIR}{Scan Index Register}
 \end{register}
	The {\sym Scan Index Register} is an autoincrementing pointer
which specifies the sequential place, within a scan, of the currently
accessed site.  At the beginning of an experiment this pointer will
normally be initialized by writing a value of 0 to it.  Since the
length of a scan is always a power of two (see {\sym End-of-Scan
Pointer}, \sect{SFR})---say, $2^n$---the $n$ low-order bits of
the {\sym SIR} will return to zero at the end of each scan. Thus, this
register does not ordinarily need to be cleared between scans.

Since the {\sym SIR} ultimately points to a \dram\ bit, its clocking
rate is geared to the accessibility of that bit as a source and/or a
destination; on data transfers between the host and \cam, it is
further constrained by the accessibility of the corresponding host
bit.  In the fastest scanning modes (modes 2 and 3 in \sect{SFR}), the
{\sym SIR} peak clock rate equals the system clock rate; in modes 0
and 1, it drops to one quarter that rate (since only one bit per
\dram\ nybble is effectively usable).  During host \io\ via the {\sym
Scan I/O Register}, operation of the scan circuitry (including the
{\sym Scan Index Register}) is enabled by the \bus\ handshake signals
(\cf{data-readiness}).
 
\section{Scan Index Permutation Register}\label{sect.PR}

 \begin{register}{120}{SIPR}{Scan Index Permutation Register}
	\compositeof
	\subreg{5}{SSA0}{Select Site Address \ 0}
	\subreg{5}{SSA1}{Select Site Address \ 1}
	\subreg{}{\ .}{}
	\subreg{}{\ .}{}
	\subreg{}{\ .}{}
	\subreg{5}{SSA23}{Select Site Address 23}
 \end{register}
	As explained in \sect{scan-permuter}, the order in which sites
are accessed during a scan is derived from the {\sym Scan Index
Register}, which is incremented by one for each scanned site. When the
24 scan index bits are directly used in their natural order as site
address bits, then the entire module is scanned as if by series of
nested loops in which the first dimension (\cf{dimensions},
\andsect{DR}) corresponds to the innermost loops and the
last to the outermost loop.

However, this order can be significantly altered by permuting the scan
index bits before using them as site address bits.  The source of each
of the 24 site address bits is specified by the value of a five-bit
{\sym Select Site Address $n$} pointer\footnote
	{These registers actually allow one to have all possible {\em
combinations with repetition}, of which permutations form a subset.
In practice, however, permutations are all that we are generally
interested in.}
	according to the following table
 \begin{equation}\label{eq.permuters-choices}
 \begin{tabular}{|l|l|}\hline
	{\sym SSA} value & \multicolumn{1}{|c|}{site address bit
source}\\\hline\hline
	$\phantom{0}$0 & bit $\phantom{0}$0 of the {\sym Scan Index Register}\\
	$\phantom{0}$1 & bit $\phantom{0}$1 of the {\sym Scan Index Register}\\
	$\phantom{0}$2 & bit $\phantom{0}$2 of the {\sym Scan Index Register}\\
	$\phantom{0}$$\vdots$\ & \quad$\vdots$\\
	23 & bit 23 of the {\sym Scan Index Register}\\\hline
	24--29 & not used\\\hline
	30 & 0\\
	31 & 1\\\hline
 \end{tabular}\;;
 \end{equation}
	note that the constant values 0 and 1 are among the possible
sources.  This is important for scanning less than the whole
space---the unused address bits are set to a constant that specifies
which part of the space is being scanned.


\section{Scan I/O Register}\label{sect.SIOR}

 \begin{register}{-{}-{}-}{SIOR}{Scan I/O Register}
 \end{register}
	 As mentioned in \sect{chip-regs}, the {\sym Scan I/O
Register} is used for accessing all or part of the \dram\ chip
connected to a given \chip, and does not have an intrinsic length.  By
setting up a scan of a certain size and shape (see \sect{SFR}),
data may be read from or written to the scanned area through the {\sym
Scan I/O Register}.

Addressing the
{\sym Scan I/O Register} starts a scan\footnote
	{At the moment of initiating a \dram\ \io\ operation via this register,
the {\sym Scan Sync Mode} (\sect{RMR}) will normally be found to be 0,
indicating that no internally-clocked scan is in progress or scheduled;
nevertheless, typically one will explicitly write to it before
performing \dram\ \io, in order to transfer the event count from the
previous scan into the {\sym Event Count Register.}}
	that is clocked by data transfer across the \bus\ (\cf{SIR}).
By appropriately setting the {\sym Source Register}s
(\sect{LASR}--\sect{ECSR}), host-generated data may be integrated into
this \bus-driven scan.  This not only allows host data to be combined
with current \dram\ data, but, depending on the options selected, it
also allows the host to write to the event counter (for testing), or
to write (for control of \cam's video interface) the data on the video
bus (\cf{}). In a similar way, a \bus\ read transaction with the {\sym
Scan I/O Register} makes a module scan (and possibly update) its data
with a timing that takes into account the bus's moment-by-moment
availability to accept data.  All {\sym Scan I/O} read operations get
their data from the display output (\cf{DSR}).

\medskip

If the {\sym Verify Write Flag} (\sect{VWR}) is set, any portion of
the \dram\ may of course be checked instead of written.


\section{Scan Format Register}\label{sect.SFR}

 \begin{register}{\ 33}{SFR}{Scan Format Register}
	\compositeof
	\subreg{2}{SM}{Scan Mode}
	\subreg{5}{ESCP}{End-of-Scan Pointer}
	\subreg{4}{ESWP}{End-of-Sweep Pointer}
	\subreg{4}{ESTP}{End-of-Stretch Pointer}
	\subreg{5}{RCL}{Refresh Cycle Length}
	\subreg{8}{SBRC}{Sweeps Between Refresh Cycles}
	\subreg{5}{ECL}{Event Counter Length}
 \end{register}
	The {\sym Scan Format Register} is used, in conjunction with the
{\sym Scan Index Permutation Register}, to set the scan format.

The {\sym Scan Mode} selects one of the four basic scan modes: mode 0
(1 bit per nibble, no pipelining), mode 1 (1 bit per nibble, with
pipelining), mode 2 (open sweep, 4 bits per nibble, with pipelining),
mode 3 (closed sweep, 4 bits per nibble, with pipelining); these are
described in \sect{}--\andsect{}.  The software should select the
fastest of these four modes of scan that is compatible with the
selected permutation (pipelining can only be done within a single
\dram\ row; no writes can be done to data that is still in the
pipeline; etc.).

The {\sym End-of-Scan Pointer} points to a carry position in the {\sym
Scan Index Register}.  As the {\sym SIR} counts during a scan, the
occurence of a carry at this position is used to indicate the
End-of-Scan condition (no more updating will take place until a new
scan is requested by the host; \cf{}).  Carry positions are numbered
the same as the bit position immediately to their right (e.g., the
carry between bits 0 and 1 is labeled 0).  Thus a value of 0 for the
{\sym End-of-Scan Pointer} indicates a scan of length 2, and in
general a value of $n$ indicates a scan of length $2^{n+1}$.  A value
of 31 selects a constant of 1 to be used as the carry (same convention
as used for {\sym Scan Index Permutation Register}), and results in a
scan of length 1.  As a mnemonic, note that this scan length actually
still follows the $2^{n+1}$ rule if we consider a five bit binary
value of 11111 (31 decimal) for the {\sym End of Scan Pointer} to be
-1 in two's complement form.

Similarly, the {\sym End-of-Sweep Pointer} points into the {\sym SIR}
to indicate an End-of-Sweep condition (\sect{}), and the {\sym
End-of-Stretch} an End-Of-Stretch condition (\sect{}).  If the length
of the stretch (or the sweep) is set to be longer than the length of
the scan, it is truncated to be the same length as the scan.

The {\sym Refresh Cycle Length} indicates the number of refreshes to
perform during each refresh cycle (refreshes are continuously
performed when scanning isn't taking place); the {\sym Sweeps Between
Refresh Cycles} indicates the number of sweeps to perform between
each refresh cycle.

The {\sym Event Counter Length} specifies the effective length of the
event counter, which may be less than 25 bits (see \sect{ECR}).  This
length will depend on the number of sites to be counted between
readings, and typically is set whenever the scan size is changed.


\section{Offset Register}\label{sect.OR}

 \begin{register}{\ 24}{OSR}{Offset Register}
 \end{register}
	As explained in \sect{}, the {\sym Offset Register} of a
\chip\ records (in a modular way) by how much the origin of the
associated layer has shifted (with respect to its initial reference
position) under the cumulative action of previous kicks.

\medskip

The layer offset is added (separately for each dimension, as specified
by the {\sym Dimension Cut Mask}, \sect{DR}) to
the site address (which normally is the same for all layers) to yield
the {\sym Physical Address} (in \dram) of the bit belonging to the
currently scanned site and to the layer in question.

To implement the gluing algorithm (\sect{}), this \dram\ bit is made
available to the data stream (\sect{}) together with the homologous
bits coming from the six adjacent modules.  Which of these six bits is
actually used depends on the $x$, $y$, and $z$ carries from the above
addition, in conjunction with the corresponding kick signs
(\sect{KR}).

\medskip

Note: the {\sym Offset Register} is not cleared by a soft
(interface-initiated) \chip-reset.  This is done to facilitate error
recovery (see {\sym IR} and {\sym DOCR}).

\section{Dimension Register}\label{sect.DR}

 \begin{register}{\ 38}{DR}{Dimension Register}
	\compositeof
	\subreg{23}{DCM}{Dimension Cut Mask}
	\subreg{5}{XDCP}{X-Dimension Cut Pointer}
	\subreg{5}{YDCP}{Y-Dimension Cut Pointer}
	\subreg{5}{ZDCP}{Z-Dimension Cut Pointer}
 \end{register}
	The {\sym Dimension Register} is used to indicate how the
simulation space is shaped into a multidimensional array.

\medskip

Specifically, the 23-bit {\sym Dimension Cut Mask} is used
to cut the site-address arithmetic chain into up to 24 slices, each
corresponding to a distinct dimension (\cf{dimensions}).

The {\sym X-Dimension Cut Pointer} specifies which of those dimensions
is to be identified with the extendible dimension $x$. As indicated in
the following table
 \begin{equation}\label{eq.xcut-choices}
 \begin{tabular}{|l|l|}\hline
	{\sym XDCP} & \multicolumn{1}{|c|}{{\sym X-Wrap} source}\\\hline\hline
	$\phantom{0}$0 & carry from bit $\phantom{0}$0\\
	$\phantom{0}$1 & carry from bit $\phantom{0}$1\\
	$\phantom{0}$2 &  carry from bit $\phantom{0}$2\\
	$\phantom{0}$$\vdots$\ & \quad$\vdots$\\
	23 &  carry from bit 23\\\hline
	24--29 & not used\\\hline
	30 & 0\\
	31 & 1\\\hline
 \end{tabular}\;,
 \end{equation}
	this pointer selects, as the source for the {\sym X-Wrap}
signal, the borrow (out of the corresponding slice) resulting from
subtracting the $x$-component of the kick from the $x$-component of
the site address. Values 30 and 31 of the {\sym Dimension Cut
Pointer}s substitute for this borrow a constant value of 0 or 1; this
is useful for testing, or for suppressing external gluing and allowing
an extendible dimension to be wrapped around within the module
(\cf{KR}).

Analogous considerations apply to the $y$ and $z$ dimensions and the
associated {\sym Dimension Cut Pointer}\,s.  Note that external gluing
is controlled by the {\sym Kick Sign}s and {\sym Kick Max Flag}s, as
well as by the {\sym Cut pointers}.
 

\section{Hardware Environment Register}\label{sect.HER}

 \begin{register}{\ 16}{HER}{Hardware Environment Register}
	\compositeof
	\subreg{1}{LPL}{LUT Pipeline Length}
	\subreg{1}{FPL}{Flywheel Pipeline Length}
	\subreg{1}{DS}{DRAM Size}
	\subreg{6}{TBD}{Tree Balancing Delay}
	\subreg{4}{TMS}{Test Mode Select}
	\subreg{1}{NBF}{Node Bypass Flag}
	\subreg{1}{SRE}{Select Read Enable}
	\subreg{1}{ALS}{Active LUT Select}
 \end{register}
	The {\sym Hardware Environment Register} contains information
about the hardware connected to the \chip---the size of the \dram, the
configuration of the \bus, pipelining information about the updating
circuitry, etc.

If the {\sym LUT Pipeline Length} is set, four bits of pipeline
delay are expected between the \sram\ address pins and the \sram\ data
pins (\sect{dram-side-pins}); otherwise, only one bit of delay is
expected.  What is normally connected between these two sets of pins
is a \sram\ lookup table which operates in a single clock cycle.

Similarly, if the {\sym Flywheel Pipeline Length} is set, four bits
of pipeline delay (rather than one) are expected in any hardware
connected between the flywheel data output pins and the flywheel data
input pins (\sect{flywheel-pins}).

The \chip\ can serve \dram{}s of two sizes, namely, either 4 or 16 Mbits;
the {\sym DRAM Size} tells the \chip\ which size is actually
in use, as follows
 \begin{equation}\label{eq.dram-size}
 \begin{tabular}{|c|c|r|}\hline
	\sym DS & \dram\ size & addr.\ lines \\\hline\hline
	0 & 4 Mbit & 10 \\
	1 & 16 Mbit & 11 \\\hline
 \end{tabular}\
 \end{equation}

If the \bus\ tree is not implemented as a balanced tree
(\cf{bus-structure}), bus data will reach certain modules earlier than
others.  The {\sym Tree Balancing Delay} specifies how much closer the
given module is to the root than the farthest module in the tree.
Since modules that are closer to the root receive their commands
earlier (by one clock cycle per tree segment), a corresponding delay
is inserted by the \chip\ hardware before the start of a sweep
(\cf{RMR}) so as to allow all modules to sweep in lockstep.  Note that
this delay is not inserted during scan-io (\sect{SIOR}), and so no use
of glue should occur during this mode, since modules will not be
scanned in lockstep.

{\sym Test Mode Select} is used to put the \chip\ into special test
modes.  Each of the 16 {\sym TMS} values selects not only a test mode,
but also a single output value that can be made available through
{\sym Multipurpose Pin}s (\cf{MPCR}).  The choices are

 \begin{equation}\label{eq.testmode}
 \begin{tabular}{|c|p{.75in}|p{1.25in}|}\hline
	\sym TMS & \multicolumn{1}{c|}{test mode} &
\multicolumn{1}{c|}{signal name}\\\hline
	0 & none & \\
	1 & none & \sym End Of Stretch Pulse \\
	2 & none & \sym End Of Sweep Pulse \\
	3 & none & \sym End Of Scan Pulse \\
	4 & & \\
	5 & & \\
	6 & & \\
	7 & & \\
	8 & & \\
	9 & & \\
	10 & & \\
	11 & & \\
	12 & & \\
	13 & & \\
	14 & & \\
	15 & & \\\hline
 \end{tabular}
 \end{equation}
The {\sym Node Bypass Flag} is used to indicate whether the internal
\bus\ node within the \chip\ should be inserted before internal use of
\bus\ signals, or whether it should be bypassed.  If one module (or
box of modules, all at the same level in the \bus\ tree) is using the
output of the internal node, while the next module or box, connected
to this one, is using the {\em input} to the internal node, then both
modules/boxes will be at the same level of the \bus; thus if we want
to build a balanced tree, we can do so using half as many external
nodes as we would otherwise require.

The {\sym Select Read Enable} bit is used when register 0, the {\sym
Module Select Register}, is read.  On such a read, the current
selection state of the \chip\ is ignored, and only \chip{}s that have
the {\sym Select Read Enable} bit set will respond (see \sect{MSR}).

According to its value, 0 or 1, the {\sym Active LUT Select} bit tells
which of the two \lut{}s (0 or 1) is currently active (cf.\ {\sym
Active LUT Toggle} in the {\sym Run Mode Register}, \sect{RMR}).
Writing this bit forces a specific \lut\ to become the active one.


\section{Multipurpose Pin Control Register}\label{sect.MPCR}

 \begin{register}{\ 10}{MPCR}{Multipurpose Pin Control Register}
	\compositeof
	\subreg{5}{MAFS}{Multipurpose A Function Select}
	\subreg{5}{MBFS}{Multipurpose B Function Select}
 \end{register}
	The {\sym Multipurpose} pins (\sect{misc-pins}) are used for
input or output signals that need appear only once per module rather
than once per \chip. Each chip of a set will handle two different
signals through its {\sym Multipurpose} pins, as instructed by the
{\sym Multipurpose Pin Control Register}.  We provide two of these
pins per chip so that we will have enough pins in a module with a
small number of \chip{}s to provide all essential signals.  This is
convenient for constructing low-budget \cam\ machines, and also for
reducing the number of \chip{}s needed to perform a complete
simulation of a working system.

There are 32 choices for the function of each of the {\sym
Multipurpose Pin}s.  For simplicity, we have exactly the same choices
available on both pins: the first four choices use the pin for input,
the rest of the choices are outputs.  The four input choices are:

 \begin{equation}\label{eq.multi-input}
 \begin{tabular}{|c|p{1.75in}|}\hline
	\sym MFS & \multicolumn{1}{c|}{Signal}\\\hline
	0 & \sym External Input \\
	1 & \sym External Interrupt \\
	2 & \sym Scan Input \\
	3 & \sym (reserved) \\\hline
 \end{tabular}
 \end{equation}

The {\sym External Input} allows an external signal to be delayed or
inverted and come out on the other {\sym Multipurpose Pin}, if it is
suitably configured as an output; the {\sym External Interrupt} allows
external hardware connected to the module to signal an interrupt (see
{\sym IER}); and the {\sym Scan Input} makes it possible to check for
intermodule scan-synchronization errors (see {\sym IER}).

\medskip

The rest of the {\sym Multipurpose Function Select} values indicate
that the corresponding {\sym Multipurpose Pin} is configured as an
output.  Each \chip\ generates all of the module signals that might be
needed: which signal is ouput to the pin is established by the {\sym
Multipurpose Function Select} according to the following table.
 \begin{equation}\label{eq.multi-output}
 \begin{tabular}{|c|p{1.75in}|}\hline
	\sym MFS & \multicolumn{1}{c|}{Signal}\\\hline
	 4 & \sym Status (Int/Scan) \\	
	 5 & \sym Node LSOUT \\
	 6 & \sym Node IOSEL \\
	 7 & \sym Node RSOUT \\
	 8 & \sym Reset (delayed) \\
	 9 & \sym SYNC (delayed) \\
	10 & \sym Enable Data Inbound \\
	11 & \sym Enable Data Outbound \\
	12 & \sym Scan Is Active \\
	13 & \sym Latch Glue Direction \\
	14 & \sym LUT0 Chip Select \\
	15 & \sym LUT0 Write Enable \\
	16 & \sym LUT1 Chip Select \\
	17 & \sym LUT1 Write Enable \\
	18 & \sym Data-Out Valid \\
	19 & \sym Unglued Data Bit \\ 
	20 & \sym Host Supplied Bit \\
	21 & \sym SABSR Selected Bit \\
	22 & \sym Display Valid \\
	23 & \sym Active LUT Output \\
	24 & \sym CAM Interrupt \\
	25 & \sym Scan Requested/Active \\
	26 & \sym External Input Inverted \\
	27 & \sym External Input Delayed \\
	28 & \sym (reserved) \\
	29 & \sym Test MUX Output \\
	30 & \sym Constant of 0 \\
	31 & \sym Constant of 1 \\\hline
 \end{tabular}
 \end{equation}

Choices 4--11 are \bus\ signals that are needed only once per module;
they are documented in \sect{bus}.  {\sym Scan Is Active} (choice 12)
can be used in conjunction with {\sym Scan Input} (choice 2) in
another module to test that periods of active scanning occur at the
same time in both modules (for this test, the scan is {\em not}
considered to be active during {\sym Scan I/O}, \cf{SIOR}).  {\sym
Latch Glue Direction} (choice 13) is a pulse (intended for use by
external glue signal buffers) that occurs just before active scanning
begins; at this time, glue lines are either pulled up to indicate
inputs, or actively driven low to indicate outputs.  Choices 14--17
control the SRAMs that constitute the two LUTs in a module.  {\sym
Data-Out Valid} (choice 18) is used in conjunction with choices
19--21, and also the {\sym LUT Address} and the {\sym Flywheel Output}
to mark valid data bits.  {\sym Display Valid} (choice 22) is used in
conjuction with choice 23, and also the {\sym Display Output} to mark
valid data bits (this timing is slightly later than {\sym Data-Out
Valid}).  {\sym CAM Interrupt} and {\sym Scan Requested} (choices 24
and 25) repeat the same information encoded in the {\sym Status}
signal (choice 4), but as two separate signals.  {\sym External Input
Inverted} (choice 26) reflects the value (inverted) of an {\sym
External Input} (choice 0) if such an input was selected at the other
{\sym Multipurpose Pin} of this \chip; similarly, {\sym External Input
Delayed} (choice 27) reflects an {\sym External Input} that has been
clocked through a single delay element.  The {\sym Test MUX Output}
(choice 29) is an output that is determined by the current test mode
(see {\sym Test Mode Select in \sect{HER}).  Finally, constants of 0
and 1 can be selected as choices 30 and 31 respectively.

\medskip

At reset time, the {\sym Multipurpose} pins are always configured as
inputs (choice 0), and are used to distinguish one \cam\ module from
all of the others (\sect{id-init}): the {\sym Module ID Register} is
set from {\sym Multipurpose Pin A} while reset is asserted.  All {\sym
Multipurpose Pin}s are weakly pulled up by internal pullups, and
therefore give 1 at reset and until configured, unless they are
explicitly pulled down.  This means that at reset, in an unbalanced
tree, all boxes except the one at the root of the tree are cut off
from the \bus\ until the root's {\sym Multipurpose Pin}s are
configured.  This distinguishes the root box from all other boxes, and
is useful in establishing a distinguished module to use as the origin
for numbering the rest (the point in a \bus\ frame at which the new
value of the {\sym Multipurpose Pin} selections become enabled is
chosen to make enabling the \bus\ work properly).


\section{Glue Pin Connectivity Register}\label{sect.GPCR}

 \begin{register}{\ 18}{GPCR}{Glue Pin Connectivity Register}
	\compositeof
	\subreg{3}{XMPC}{XM-Pin Connect}
	\subreg{3}{XPPC}{XP-Pin Connect}
	\subreg{3}{YMPC}{YM-Pin Connect}
	\subreg{3}{YPPC}{YP-Pin Connect}
	\subreg{3}{ZMPC}{ZM-Pin Connect}
	\subreg{3}{ZPPC}{ZP-Pin Connect}
 \end{register}
	The {\sym Glue Pin Connectivity Register} is written at
setup time in order to determine what logical interconnection
should be associated with the physical interconnection provided by
each of the six glue pins (\sect{glue-pins}).

One use of this configuration flexibility is described in
\sect{block-improved}.  More drastic reconfigurations are possible.
Normally the glue pins define a three-dimensional array of modules,
interconnected as described in \chapt{block-structure}.  However, by
appropriately arranging the connectivity between modules, one can
connect them as a two-dimensional array (physically folded
back-and-forth over itself, with the folds piling up in the third
dimension), or even as a one-dimensional chain.

\medskip

Each of the six connectivity registers corresponds to a {\em physical}
glue port (\chip\ pins {\sym XM}, {\sym XP}, {\sym YM}, {\sym YP},
{\sym ZM}, {\sym ZP}) and associates with it a {\em logical} glue port
($x_-$, $x_+$, $y_-$, $y_+$, $z_-$, $z_+$, as explained in \sect{}) or
one of the constants 0 and 1.

Whenever the kick sign for dimension $x$ is positive, thus indicating
that logical port $x_+$ should be an {\em output} (\cf{}), then
any physical port that has been associated with $x_+$ by the {\sym
Glue Pin Connectivity Register} will be configured as an output and will
display the value of $x_+$; if more than one physical port is
associated with the same logical port, they will all behave alike.

When the kick sign is negative, thus indicating that logical port
$x_+$ should be an {\em input}, then any physical port associated with
$x_+$ will be configured as an input and will contribute a source of
data for $x_+$: if more than one physical port is associated with
$x_+$, their values will be {\sc or}ed before being passed on to
$x_+$.

Finally, if a physical port is associated with a constant, then it
will always be an output and display that constant.  The constants are
used during initialization for determining the physical connectivity
of the machine and initializing each module's ID (\sect{id-init}).

\medskip

The value of {\sym XM-Pin Connect} determines the logical glue ports
(or the constant) associated with the corresponding to physical port
{\sym XM} according to the following table (and similarly for the
other five ports)
 \begin{equation}\label{eq.connectivity-choices}
 \begin{tabular}{|cc|c|}\hline
	\multicolumn{2}{|c|}{\sym XMPC}&\multicolumn{1}{|c|}{logical port}\\
	octal & binary &\multicolumn{1}{|c|}{or constant}\\\hline\hline
	0 & 00 0 & $x_-$\\
	1 & 00 1 & $x_+$\\
	2 & 01 0 & $y_-$\\
	3 & 01 1 & $y_+$\\
	4 & 10 0 & $z_-$\\
	5 & 10 1 & $z_+$\\\hline
	6 & 11 0 & 0\\
	7 & 11 1 & 1\\\hline
 \end{tabular}\
 \end{equation}

Each glue pin is internally pulled up by a resistor to a logical 1, so
that, when configured as an input and not otherwise driven, it will
sense a logical 1; this feature is used during module ID initialization
(\sect{id-init}).

Any glue pin which is not configured as a constant will act as an input
whenever the scan is not active.


\section{Module ID Register}\label{sect.MIDR}

\catcode`\@=11
\immediate\write\@auxout{\string
	\newlabel{sample-section}{{\arabic{section}}{\thepage}}}
\catcode`\@=12

 \begin{register}{\ \ 1}{MIDR}{Module ID Register}
 \end{register}
	Each \cam\ module has a unique {\em module ID}, which is
primarily used for module selection (\sect{modselect}); this ID is
assigned during hardware initialization (\sect{id-init}).  Each of the
16 \chip{}s of a set holds one bit of the module ID, in the {\sym
Module ID Register} ({\sym MIDR}).

At reset, the {\sym MIDR} is set to the value of the {\sym Multipurpose 
Pin A} (see \sect{id-init} for details).


\section{Group ID Register}\label{sect.GIDR}

 \begin{register}{\ \ 1}{GIDR}{Group ID Register}
 \end{register}
	Besides the module ID, which is unique for each chip
(\sect{MIDR}), each \cam\ module has also a {\em group ID},
which is primarily used for module selection (see \sect{modselect})
when one wants to address a whole group of modules rather than a
single one (see \sect{modselect}). Each of the 16 \chip{}s of a set
holds one bit of the group ID, in the {\sym Group ID Register} ({\sym
GIDR}).

Note that by using the `dont care' selection code (see table
\eq{selection-codes.rpt}) in some positions of the {\sym Module Select
Register} (\sect{SR}), one can select different groups
of modules based on data contained in different portions of the {\sym
GIDR}.


\section{Interrupt Enable Register}\label{sect.IER}

 \begin{register}{\ \ 10}{IER}{Interrupt Enable Register}
	\compositeof
	\subreg{1}{BPIE}{Bus Parity Interrupt Enable}
	\subreg{1}{BCIE}{Bus Contention Interrupt Enable}
	\subreg{1}{GCIE}{Glue Contention Interrupt Enable}
	\subreg{1}{VCIE}{Video Contention Interrupt Enable}
	\subreg{1}{MCIE}{Multi Contention Interrupt Enable}
	\subreg{1}{SSIE}{Skewed Scan Interrupt Enable}
	\subreg{1}{XHIE}{External Hardware Interrupt Enable}
	\subreg{1}{RLIE}{Register Length Interrupt Enable}
	\subreg{1}{URIE}{Unknown Register Interrupt Enable}
	\subreg{1}{ISIE}{Invalid SYNC Interrupt Enable}
 \end{register}
	The {\sym Interrupt Enable Register} is a collection of bits
that individually enable the interrupts described in the following
section, devoted to the {\sym Interrupt Flags Register}. An interrupt
will be recognized only if the corresponding {\sym IER} bit is set.
Since these interrupts all signal error conditions, their enables
should normally all be on.  Even in chips which don't have External
Hardware or Scan Input attached, the corresponding interrupts should
not signal an error, and so can be left enabled.

\medskip

An additional interrupt enable flag, associated with the verify-write
mode, is discussed in \sect{VWR}.

\section{Interrupt Flags Register}\label{sect.IFR}

 \begin{register}{\ \ 10}{IFR}{Interrupt Flags Register}
	\compositeof
	\subreg{1}{BPIF}{Bus Parity Interrupt Flag}
	\subreg{1}{BCIF}{Bus Contention Interrupt Flag}
	\subreg{1}{GCIF}{Glue Contention Interrupt Flag}
	\subreg{1}{VCIF}{Video Contention Interrupt Flag}
	\subreg{1}{MCIF}{Multi Contention Interrupt Flag}
	\subreg{1}{SSIF}{Skewed Scan Interrupt Flag}
	\subreg{1}{XHIF}{External Hardware Interrupt Flag}
	\subreg{1}{RLIF}{Register Length Interrupt Flag}
	\subreg{1}{URIF}{Unknown Register Interrupt Flag}
	\subreg{1}{ISIF}{Invalid SYNC Interrupt Flag}
 \end{register}
	The {\sym Interrupt Flags Register} is a collection of one bit
flags, each of which is set when the corresponding error condition is
detected (see \sect{cbus-interrupts} for details).

When an interrupt condition is detected by the \chip\ hardware, if the
corresponding enable flag is set (\sect{IER}) an interrupt will be
sent via the \bus\ to the \cam\ interface, which in turn will
interrupt the host. Once the interrupt reaches the interface, further
interface operation is suspended until the host restarts it.

An additional interrupt flag, associated with the verify-write
mode, is discussed in \sect{VWR}.

\medskip

The contention interrupts indicate that a signal sampled at the output
of a bussed or bidirectional pin did not agree with the value that was
being driven.

A {\sym Bus Parity} error is indicated if the last completed \bus\ 
transaction didn't have overall odd parity, including the final Parity
bit that was sent.

A {\sym Skewed Scan} interrupt is signalled if the {\sym Scan Input}
is used, and disagrees with the internally generated {\sym Scan is
Active} signal.

An {\sym External Hardware Interrupt} is signalled if the {\sym
External Interrupt Input} is used, and it goes low.

A {\sym Register Length Interrupt} is signalled if a Register is
written by the host with an incorrect length, or if a register is read
by the host with too short a length.

An {\sym Unkown Register Interrupt} occurs if an attempt is made by
the host to access register 29, 30, or 31.

An {\sym Invalid SYNC Interrupt} is signalled when one of the 4-bit
packets of video-SYNC timing information (see \sect{RMR}) coming in on
the SYNC input of the \chip\ (\cf{}) fails to have even parity.

\medskip

Note: the {\sym Interrupt Flags Register} is not cleared by a soft
(interface-initiated) \chip-reset.  This is done to facilitate error
recovery (see {\sym OSR} and {\sym DOCR}).


\section{Verify Write Register}\label{sect.VWR}

 \begin{register}{\ \ 3}{VWR}{Verify Write Register}
	\compositeof
	\subreg{1}{VWE}{Verify Write Enable}
	\subreg{1}{VWIE}{Verify Write Interrupt Enable}
	\subreg{1}{VWIF}{Verify Write Interrupt Flag}
 \end{register}
	With an ordinary write frame, the transmitted data overwrite
the contents of the addressed register (or the contents of the
addressed \dram\ or \sram\ area, if the register is an I/O register).
The {\sym Verify Write Register} allows one to control a special {\em
verify-write} mode, where the transmitted data are simply compared
with this contents without changing it. This mode is enabled by
turning on the {\sym Verify Write Enable}.  Verify write is always
disabled while writing to the {\sym VWE} register itself, to make it
possible to turn the mode on and off.

In verify-write mode, an interrupt condition is signaled---by setting
the {\sym Verify Write Interrupt Flag}---if data written to a register
disagree with its contents.  Verify-write errors are only
signaled at the {\em end} of a data transfer (see the discussion of
data transfer errors in \sect{cbus-interrupts}).

Setting the {\sym Verify Write Interrupt Enable} allows the interrupt
condition to generate an actual interrupt. Enabling the verify-write
mode on a given \chip\ without enabling the corresponding interrupt
provides a way of {\em disabling} the writing of data on that chip.
In this way, one can ``write-protect'' one or more of the sixteen
layers, to change registers on some chips in the module and not on
others.  Note that this {\em write-per-bit} technique cannot be used
with the \lut{}s.


\section{DRAM Ones Count Register}

 \begin{register}{\ 16}{DOCR}{DRAM Ones Count Register}
	\compositeof
	\subreg{8}{LDOC}{Low DRAM Ones Count}
	\subreg{8}{HDOC}{High DRAM Ones Count}
 \end{register}
	A \dram\ {\em ones counter} is an up/down counter that is
cleared, together with the \dram, at initialization time.  From then
on, each time a 0 in the \dram\ is changed to a 1, the counter is
incremented; each time 1 goes to 0, decremented; otherwise, it remains
unchanged.  Thus the counter should always reflect the number of ones
in the \dram\ (modulo the counter's size).

By using the event counter to occasionally count all locations in the
\dram, and comparing this count with that recoreded by the ones
counter, it should be possible to detect (with a high probability)
soft errors in the \dram.

\medskip

Each \chip\ has one \dram\ chip attached to it. The {\sym DRAM Ones
Count Register} consists of two independent {\sym DRAM Ones Count}s
({\sym LDOC} and {\sym HDOC}) that are associated repectively with the
low and high halves of this \dram.

By having separate counts for the two halves of the \dram, it becomes
possible to effectively handle errors on a large machine.  We split
the machine into two halves, each employing half of each \dram\ chip,
and both performing the same computation.  In the case of a miscompare
between the operation of the two halves, the {\sym DRAM Ones Count}s
make it likely that we can resolve which of the two halves got an
error, and then correct the errorneous data from the other half.

\medskip

Note: the {\sym DRAM Ones Count Register} is not cleared by a soft
(interface-initiated) \chip-reset.  This is done to facilitate error
recovery (see {\sym OSR} and {\sym IR}).

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