\begin {register}{\ \ 3}{MSR}{Module Select Register}{0}
\end {register}
\begin {register}{\ \ 6}{RMR}{Run Mode Register}{1}
\hline \hline 
\subreg {2}{SSM}{Scan Sync Mode}
\subreg {1}{RT}{Run Type}
\subreg {1}{ECT}{Event Count Transfer}
\subreg {1}{RPK}{Repeat Previous Kick}
\subreg {1}{ALT}{Active LUT Toggle}
\end {register}
\begin {register}{\ 30}{KR}{Kick Register}{2}
\hline \hline 
\subreg {24}{KA}{Kick Amount}
\subreg {1}{XKS}{X-Kick Sign}
\subreg {1}{YKS}{Y-Kick Sign}
\subreg {1}{ZKS}{Z-Kick Sign}
\subreg {1}{XKMF}{X-Kick Max Flag}
\subreg {1}{YKMF}{Y-Kick Max Flag}
\subreg {1}{ZKMF}{Z-Kick Max Flag}
\end {register}
\begin {register}{\ \ 5}{SABSR}{Site Address Bit Select Register}{3}
\end {register}
\begin {register}{\ \ 6}{LASR}{LUT Address Source Register}{4}
\hline \hline 
\subreg {2}{LAS}{LUT Address Select}
\subreg {4}{LAM}{LUT Address Map}
\end {register}
\begin {register}{\ \ 6}{FOSR}{Flywheel Output Source Register}{5}
\hline \hline 
\subreg {2}{FOS}{Flywheel Output Select}
\subreg {4}{FOM}{Flywheel Output Map}
\end {register}
\begin {register}{\ \ 6}{SDSR}{Site Data Source Register}{6}
\hline \hline 
\subreg {2}{SDS}{Site Data Select}
\subreg {4}{SDM}{Site Data Map}
\end {register}
\begin {register}{\ \ 6}{ECSR}{Event Counter Source Register}{7}
\hline \hline 
\subreg {2}{ECS}{Event Counter Select}
\subreg {4}{ECM}{Event Counter Map}
\end {register}
\begin {register}{\ \ 6}{DSR}{Display Source Register}{8}
\hline \hline 
\subreg {2}{DDS}{Display Data Select}
\subreg {4}{DDM}{Display Data Map}
\end {register}
\begin {register}{\ \ 1}{SSR}{Show Scan Register}{9}
\end {register}
\begin {register}{-{}-{}-}{ECR}{Event Count Register}{10}
\end {register}
\begin {register}{\ 16}{LIR}{LUT Index Register}{11}
\end {register}
\begin {register}{\ \ 5}{LIPR}{LUT Index Permutation Register}{12}
\end {register}
\begin {register}{-{}-{}-}{LIOR}{LUT I/O Register}{13}
\end {register}
\begin {register}{\ 24}{SIR}{Scan Index Register}{14}
\end {register}
\begin {register}{120}{SIPR}{Scan Index Permutation Register}{15}
\hline \hline 
\subreg {5}{SSA0}{Select Site Address \ 0}
\subreg {5}{SSA1}{Select Site Address \ 1}
\subreg {}{\ .}{}
\subreg {}{\ .}{}
\subreg {}{\ .}{}
\subreg {5}{SSA23}{Select Site Address 23}
\end {register}
\begin {register}{-{}-{}-}{SIOR}{Scan I/O Register}{16}
\end {register}
\begin {register}{\ 35}{SFR}{Scan Format Register}{17}
\hline \hline 
\subreg {2}{SM}{Scan Mode}
\subreg {5}{ESC}{End-of-Scan}
\subreg {4}{ESW}{End-of-Sweep}
\subreg {4}{EST}{End-of-Stretch}
\subreg {5}{SBRC}{Sweeps Between Refresh Cycles}
\subreg {8}{RCL}{Refresh Cycle Length}
\subreg {5}{ECL}{Event Counter Length}
\subreg {2}{STM}{Stretch Magnification}
\end {register}
\begin {register}{\ 24}{OSR}{Offset Register}{18}
\end {register}
\begin {register}{\ 38}{DR}{Dimension Register}{19}
\hline \hline 
\subreg {23}{DCM}{Dimension Cut Mask}
\subreg {5}{XDCP}{X-Dimension Cut Pointer}
\subreg {5}{YDCP}{Y-Dimension Cut Pointer}
\subreg {5}{ZDCP}{Z-Dimension Cut Pointer}
\end {register}
\begin {register}{\ 16}{HER}{Hardware Environment Register}{20}
\hline \hline 
\subreg {1}{LPL}{LUT Pipeline Length}
\subreg {1}{FPL}{Flywheel Pipeline Length}
\subreg {1}{DCS}{DRAM Column Size}
\subreg {6}{TBD}{Tree Balancing Delay}
\subreg {4}{TMS}{Test Mode Select}
\subreg {1}{NBF}{Node Bypass Flag}
\subreg {1}{SRE}{Select Read Enable}
\subreg {1}{ALS}{Active LUT Select}
\end {register}
\begin {register}{\ 10}{MPCR}{Multipurpose Pin Control Register}{21}
\hline \hline 
\subreg {5}{MAFS}{Multipurpose A Function Select}
\subreg {5}{MBFS}{Multipurpose B Function Select}
\end {register}
\begin {register}{\ 18}{GPCR}{Glue Pin Connectivity Register}{22}
\hline \hline 
\subreg {3}{XMPC}{XM-Pin Connect}
\subreg {3}{XPPC}{XP-Pin Connect}
\subreg {3}{YMPC}{YM-Pin Connect}
\subreg {3}{YPPC}{YP-Pin Connect}
\subreg {3}{ZMPC}{ZM-Pin Connect}
\subreg {3}{ZPPC}{ZP-Pin Connect}
\end {register}
\begin {register}{\ \ 1}{MIDR}{Module ID Register}{23}
\end {register}
\begin {register}{\ \ 1}{GIDR}{Group ID Register}{24}
\end {register}
\begin {register}{\ \ 10}{IER}{Interrupt Enable Register}{25}
\hline \hline 
\subreg {1}{BPIE}{Bus Parity Interrupt Enable}
\subreg {1}{BCIE}{Bus Contention Interrupt Enable}
\subreg {1}{GCIE}{Glue Contention Interrupt Enable}
\subreg {1}{MAIE}{Multi-A Contention Interrupt Enable}
\subreg {1}{MBIE}{Multi-B Contention Interrupt Enable}
\subreg {1}{SSIE}{Skewed Scan Interrupt Enable}
\subreg {1}{XHIE}{External Hardware Interrupt Enable}
\subreg {1}{RLIE}{Register Length Interrupt Enable}
\subreg {1}{URIE}{Unknown Register Interrupt Enable}
\subreg {1}{ISIE}{Invalid SYNC Interrupt Enable}
\end {register}
\begin {register}{\ \ 10}{IFR}{Interrupt Flags Register}{26}
\hline \hline 
\subreg {1}{BPIF}{Bus Parity Interrupt Flag}
\subreg {1}{BCIF}{Bus Contention Interrupt Flag}
\subreg {1}{GCIF}{Glue Contention Interrupt Flag}
\subreg {1}{MAIF}{Multi-A Contention Interrupt Flag}
\subreg {1}{MBIF}{Multi-B Contention Interrupt Flag}
\subreg {1}{SSIF}{Skewed Scan Interrupt Flag}
\subreg {1}{XHIF}{External Hardware Interrupt Flag}
\subreg {1}{RLIF}{Register Length Interrupt Flag}
\subreg {1}{URIF}{Unknown Register Interrupt Flag}
\subreg {1}{ISIF}{Invalid SYNC Interrupt Flag}
\end {register}
\begin {register}{\ \ 3}{VWR}{Verify Write Register}{27}
\hline \hline 
\subreg {1}{VWE}{Verify Write Enable}
\subreg {1}{VWIE}{Verify Write Interrupt Enable}
\subreg {1}{VWIF}{Verify Write Interrupt Flag}
\end {register}
\begin {register}{\ 16}{DOCR}{DRAM Ones Count Register}{28}
\hline \hline 
\subreg {8}{LDOC}{Low DRAM Ones Count}
\subreg {8}{HDOC}{High DRAM Ones Count}
\end {register}
