                                                     C:\CAM8\TESTDEV\IOIDB.RPT
MAX+PLUS Compiler Report File
 Version 2.6 09/10/90

***** Design compiled without errors

CAM8 IOIDB
Turbo: ON
Security: OFF

                                  EPM5032DC-1 
                                   - - - - -
                             GND -|1      28|- AS 
                             GND -|2      27|- BG 
                            ack0 -|3      26|- RESERVED 
                            ack1 -|4      25|- intreq 
                            ack2 -|5      24|- addr21 
                              BR -|6      23|- ldram 
                             VCC -|7      22|- VCC 
                             GND -|8      21|- GND 
                        complete -|9      20|- drram 
                          draddr -|10     19|- size2 
                          drprom -|11     18|- size1 
                            read -|12     17|- size0 
                             ram -|13     16|- reset 
                          sysclk -|14     15|- sel 
                                   - - - - -

                                                     C:\CAM8\TESTDEV\IOIDB.RPT
** RESOURCE USAGE **                                                  

Logic Array Block     Macrocells    I/O Pins    Expanders   

A:     MC1 - MC32    25/32( 78%)  15/16( 93%)  32/64( 50%) 

Total dedicated input pins used:     6/  8 ( 75%)
Total I/O pins used:                15/ 16 ( 93%)
Total macrocells used:              25/ 32 ( 78%)
Total expanders used:               32/ 64 ( 50%)

Total input pins required:           7
Total output pins required:          7
Total bidirectional pins required:   7
Total macrocells required:          25
Total expanders in database:        16

Synthesized macrocells:              0/ 32 (  0%)


                                                     C:\CAM8\TESTDEV\IOIDB.RPT
** FILE HIERARCHY **                                                  





|MASTER:44|
|SLAVE:59|

                                                     C:\CAM8\TESTDEV\IOIDB.RPT
** INPUTS **                                                          

                               Expanders     Fan-In
 Pin  MCell  LAB  Primitive  Total  Shared  INP  FBK  Name
   3    (1)  (A)      INPUT     2     0       0    0  ack0
   4    (3)  (A)      INPUT     2     0       0    0  ack1
   5    (5)  (A)      INPUT     2     0       0    0  ack2
  24   (27)  (A)      INPUT     2     0       0    0  addr21
  28      -   -       INPUT     0     0       0    0  AS
  27      -   -       INPUT     0     0       0    0  BG
  13      -   -       INPUT     0     0       0    0  ram
  12   (15)  (A)      INPUT     2     0       0    0  read
  16      -   -       INPUT     0     0       0    0  reset
  15      -   -       INPUT     0     0       0    0  sel
  17   (17)  (A)      INPUT     2     0       0    0  size0
  18   (19)  (A)      INPUT     2     0       0    0  size1
  19   (21)  (A)      INPUT     2     0       0    0  size2
  14      -   -       INPUT     0     0       0    0  sysclk

                                                     C:\CAM8\TESTDEV\IOIDB.RPT
** OUTPUTS **                                                         

                               Expanders     Fan-In
 Pin  MCell  LAB  Primitive  Total  Shared  INP  FBK  Name
   3      1    A      STATE     1     1       0    4  ack0
   4      3    A       AND2     1     1       0    2  ack1
   5      5    A      STATE     1     1       0    4  ack2
   6      7    A     OUTPUT     0     0       0    4  BR
   9      9    A     OUTPUT     0     0       4    4  complete
  10     11    A     OUTPUT     0     0       0    4  draddr
  11     13    A     OUTPUT     0     0       0    4  drprom
  20     23    A     OUTPUT     0     0       0    4  drram
  25     29    A        GND     0     0       0    1  intreq
  23     25    A     OUTPUT     0     0       0    4  ldram
  12     15    A        VCC     0     0       0    1  read
  17     17    A        GND     0     0       0    1  size0
  18     19    A        VCC     0     0       0    1  size1
  19     21    A        VCC     0     0       0    1  size2

                                                     C:\CAM8\TESTDEV\IOIDB.RPT
** BURIED LOGIC **                                                    

                               Expanders     Fan-In
 Pin  MCell  LAB  Primitive  Total  Shared  INP  FBK  Name
   -     32    A        DFF     0     0       2    0  delAS
   -     26    A        DFF     6     1       6    4  |themaster|q0
   -     24    A        DFF     4     1       6    3  |themaster|q1
   -     22    A        DFF     0     0       6    3  |themaster|q2
   -     30    A        DFF     0     0       3    3  |themaster|q3
   -     14    A        DFF     0     0       2    4  |theslave|did_write
   -     20    A        DFF     2     1       9    4  |theslave|q0
   -     18    A        DFF     0     0       8    4  |theslave|q1
   -     16    A        DFF     0     0       8    4  |theslave|q2
   -     12    A        DFF     5     1       9    4  |theslave|q3
   -     28    A        DFF     0     0       3    4  |theslave|the_intreq

                                                     C:\CAM8\TESTDEV\IOIDB.RPT
** STATE MACHINE ASSIGNMENTS **                                       


|themaster|master: MACHINE
	OF BITS ( _MC030, _MC022, _MC024, _MC026 )
	WITH STATES (
	   Powerup = B"0000", 
	   Request = B"0001", 
	  BusGranted = B"1001", 
	  BusOwned = B"1010", 
	     Word1 = B"1011", 
	     Word2 = B"1100", 
	     Word3 = B"1101", 
	   Recover = B"0010", 
	  Recover2 = B"0011", 
	  Recover3 = B"0100"
);


|theslave|slave: MACHINE
	OF BITS ( _MC012, _MC016, _MC018, _MC020 )
	WITH STATES (
	      Idle = B"0000", 
	   PrmAcc1 = B"0001", 
	   PrmAcc2 = B"0100", 
	   RamAcc1 = B"0101", 
	   RamWrt1 = B"0110", 
	  SizeErr1 = B"1000", 
	  IdleAcks = B"1001", 
	  PrmDrive = B"1010", 
	   PrmWrt1 = B"1011", 
	  RamDrive = B"1100"
);


                                                     C:\CAM8\TESTDEV\IOIDB.RPT
** MACROCELL INTERCONNECTION CROSS REFERENCE **                       

        M M M M M M M M M M M M M M M M M M M M M M M M M 
        C C C C C C C C C C C C C C C C C C C C C C C C C 
        1 3 5 7 9 3 1 1 2 2 2 1 1 1 2 2 2 2 3 1 2 1 1 1 2 
        | | | | | 2 1 3 3 9 5 5 7 9 1 6 4 2 0 4 0 8 6 2 8 
        | | | | | | | | | | | | | | | | | | | | | | | | | | Name
MC1  -> - - - - - - - - - - - - - - - - - - - - - - - - - | ack0
MC3  -> - - - - - - - - - - - - - - - - - - - - - - - - - | ack1
MC5  -> - - - - - - - - - - - - - - - - - - - - - - - - - | ack2
MC7  -> - - - - - - - - - - - - - - - - - - - - - - - - - | BR
MC9  -> - - - - - - - - - - - - - - - - - - - - - - - - - | complete
MC32 -> - - - - - - - - - - - - - - - - - - - - * * * * - | delAS
MC11 -> - - - - - - - - - - - - - - - - - - - - - - - - - | draddr
MC13 -> - - - - - - - - - - - - - - - - - - - - - - - - - | drprom
MC23 -> - - - - - - - - - - - - - - - - - - - - - - - - - | drram
MC29 -> - - - - - - - - - - - - - - - - - - - - - - - - - | intreq
MC25 -> - - - - - - - - - - - - - - - - - - - - - - - - - | ldram
MC15 -> - - - - - - - - - - - - - - - - - - - - - - - - - | read
MC17 -> - - - - - - - - - - - - - - - - - - - - - - - - - | size0
MC19 -> - - - - - - - - - - - - - - - - - - - - - - - - - | size1
MC21 -> - - - - - - - - - - - - - - - - - - - - - - - - - | size2
MC26 -> - - - * * - * - - - - - - - - * * * * - - - - - - | |themaster|q0
MC24 -> - - - * * - * - - - - - - - - * * * * - - - - - - | |themaster|q1
MC22 -> - - - * * - * - - - - - - - - * * * * - - - - - - | |themaster|q2
MC30 -> - - - * * - * - - - - * * * * * * * * - - - - - - | |themaster|q3
MC14 -> - - - - - - - - - - - - - - - * - - - * - - - - - | |theslave|did_write
MC20 -> * - * - - - - * * - * - - - - - - - - * * * * * * | |theslave|q0
MC18 -> * - * - - - - * * - * - - - - - - - - * * * * * * | |theslave|q1
MC16 -> * * * - - - - * * - * - - - - - - - - * * * * * * | |theslave|q2
MC12 -> * * * - - - - * * - * - - - - - - - - * * * * * * | |theslave|q3
MC28 -> - - - - - - - - - * - - - - - - - - - - - - - - * | |theslave|the_intreq

@3   -> - - - - * - - - - - - - - - - * * * - - - - - - - | ack0
@4   -> - - - - * - - - - - - - - - - * * * - - - - - - - | ack1
@5   -> - - - - * - - - - - - - - - - * * * - - - - - - - | ack2
@24  -> - - - - - - - - - - - - - - - - - - - - - - - - * | addr21
@28  -> - - - - - * - - - - - - - - - - - - - - * * * * - | AS
@27  -> - - - - * - - - - - - - - - - * * * * - - - - - - | BG
@13  -> - - - - - - - - - - - - - - - - - - - - * - * * - | ram
@12  -> - - - - - - - - - - - - - - - - - - - - * * - * - | read
@16  -> - - - - - - - - - - - - - - - * * * * * * * * * * | reset
@15  -> - - - - - - - - - - - - - - - - - - - - * * * * - | sel
@17  -> - - - - - - - - - - - - - - - - - - - - * * * * - | size0
@18  -> - - - - - - - - - - - - - - - - - - - - * * * * - | size1
@19  -> - - - - - - - - - - - - - - - - - - - - * * * * - | size2
@14  -> - - - - - * - - - - - - - - - * * * * * * * * * * | sysclk

                                                     C:\CAM8\TESTDEV\IOIDB.RPT
** EQUATIONS **                                                       








BG       : INPUT;
sysclk   : INPUT;
reset    : INPUT;
AS       : INPUT;
sel      : INPUT;
ram      : INPUT;
addr21   : INPUT;

ack0     = TRI(  _MC001,  _EQ001);
 _MC001  = MCELL(  _EQ002 $  VCC );
  _EQ002 =  _MC012 & !_MC016 & !_MC018 & !_MC020;
  _EQ001 =  _X001;
  _X001  = EXP( !_MC012 & !_MC016 );

ack1     = TRI(  _MC003,  _EQ003);
 _MC003  = MCELL(  _EQ004 $  VCC );
  _EQ004 = !_MC012 &  _MC016;
  _EQ003 =  _X001;

ack2     = TRI(  _MC005,  _EQ005);
 _MC005  = MCELL(  _EQ006 $  VCC );
  _EQ006 =  _MC012 & !_MC016 &  _MC018 &  _MC020;
  _EQ005 =  _X001;

BR       =  _MC007;
 _MC007  = MCELL(  _EQ007 $  VCC );
  _EQ007 = !_MC022 & !_MC024 &  _MC026 & !_MC030;

complete =  _MC009;
 _MC009  = MCELL(  _EQ008 $  GND );
  _EQ008 =  ack0 &  ack1 & !ack2 & !BG &  _MC022 & !_MC024 &  _MC026 & 
              _MC030;

draddr   =  _MC011;
 _MC011  = MCELL(  _EQ009 $  VCC );
  _EQ009 = !_MC022 & !_MC024 &  _MC026 &  _MC030;

%  |theslave|q3  % 
 _MC012  = DFF(  _EQ010 $  _EQ011,  sysclk,  reset,  VCC );
  _EQ010 = !_MC012 & !_MC016 & !_MC018 & !size2 &  _X002 &  _X003
         # !_MC012 & !_MC016 & !_MC018 &  _X004
         # !_MC016 & !_MC018 &  _MC020;
  _X002  = EXP( !ram & !read );
  _X003  = EXP(  size0 &  size1 );
  _X004  = EXP( !AS & !delAS & !sel );
  _EQ011 =  _X005 &  _X006;
  _X005  = EXP(  _MC012 &  _MC016 );
  _X006  = EXP(  _MC012 &  _MC018 & !_MC020 );

drprom   =  _MC013;
 _MC013  = MCELL(  _EQ012 $  VCC );
  _EQ012 =  _MC012 & !_MC016 &  _MC018 & !_MC020
         # !_MC012 & !_MC016 & !_MC018 &  _MC020
         # !_MC012 &  _MC016 & !_MC018 & !_MC020;

%  |theslave|did_write  % 
 _MC014  = DFF(  _MC014 $  _EQ013,  sysclk,  reset,  VCC );
  _EQ013 =  _MC012 & !_MC016 &  _MC018 &  _MC020;

read     = TRI(  _MC015,  _MC030);
 _MC015  = MCELL(  VCC $  GND );

%  |theslave|q2  % 
 _MC016  = DFF(  _EQ014 $  GND,  sysclk,  reset,  VCC );
  _EQ014 = !AS & !delAS & !_MC012 & !_MC016 & !_MC018 &  ram & !sel & !size1 & 
             !size2
         # !AS & !delAS & !_MC012 & !_MC016 & !_MC018 &  ram & !sel & !size0 & 
             !size2
         # !_MC012 & !_MC018 &  _MC020;

size0    = TRI(  _MC017,  _MC030);
 _MC017  = MCELL(  GND $  GND );

%  |theslave|q1  % 
 _MC018  = DFF(  _EQ015 $  GND,  sysclk,  reset,  VCC );
  _EQ015 = !AS & !delAS & !_MC012 & !_MC018 & !_MC020 & !read & !sel & !size1 & 
             !size2
         # !AS & !delAS & !_MC012 & !_MC018 & !_MC020 & !read & !sel & !size0 & 
             !size2
         # !_MC012 &  _MC016 & !_MC018 & !_MC020;

size1    = TRI(  _MC019,  _MC030);
 _MC019  = MCELL(  VCC $  GND );

%  |theslave|q0  % 
 _MC020  = DFF(  _EQ016 $  _EQ017,  sysclk,  reset,  VCC );
  _EQ016 = !AS & !delAS & !_MC016 & !_MC018 & !_MC020 & !sel & !size2 & 
              _X003 &  _X007
         # !_MC012 &  _MC016 &  _MC018 & !_MC020
         #  _MC012 & !_MC016 & !_MC018 & !_MC020;
  _X007  = EXP(  ram & !read );
  _EQ017 =  _MC012 & !_MC016 &  _MC018 &  _MC020;

size2    = TRI(  _MC021,  _MC030);
 _MC021  = MCELL(  VCC $  GND );

%  |themaster|q2  % 
 _MC022  = DFF(  _EQ018 $  _MC022,  sysclk,  reset,  VCC );
  _EQ018 =  ack0 &  ack1 & !ack2 & !BG & !_MC022 &  _MC024 &  _MC026 & 
              _MC030
         #  ack0 &  ack1 & !ack2 &  _MC022 & !_MC024 &  _MC026 &  _MC030
         #  BG &  _MC022 & !_MC024 &  _MC030;

drram    =  _MC023;
 _MC023  = MCELL(  _EQ019 $  VCC );
  _EQ019 = !_MC012 &  _MC016 & !_MC018 &  _MC020
         #  _MC012 &  _MC016 & !_MC018 & !_MC020;

%  |themaster|q1  % 
 _MC024  = DFF(  _EQ020 $ !_MC024,  sysclk,  reset,  VCC );
  _EQ020 =  _X008 &  _X009 &  _X010 &  _X011;
  _X008  = EXP(  BG & !_MC022 &  _MC024 &  _MC030 );
  _X009  = EXP( !_MC022 & !_MC024 &  _MC026 &  _MC030 );
  _X010  = EXP(  ack0 &  ack1 & !ack2 & !_MC022 &  _MC024 &  _MC026 &  _MC030 );
  _X011  = EXP(  ack0 &  ack1 & !ack2 & !BG & !_MC024 &  _MC026 &  _MC030 );

ldram    =  _MC025;
 _MC025  = MCELL(  _EQ021 $  VCC );
  _EQ021 = !_MC012 &  _MC016 &  _MC018 & !_MC020;

%  |themaster|q0  % 
 _MC026  = DFF( !_MC026 $  _EQ022,  sysclk,  reset,  VCC );
  _EQ022 =  _X009 &  _X012 &  _X013 &  _X014 &  _X015 &  _X016;
  _X012  = EXP(  ack0 &  ack1 & !ack2 & !BG &  _MC022 & !_MC024 &  _MC030 );
  _X013  = EXP(  ack0 &  ack1 & !ack2 & !BG & !_MC022 &  _MC024 &  _MC030 );
  _X014  = EXP(  _MC014 & !_MC022 & !_MC024 & !_MC026 & !_MC030 );
  _X015  = EXP(  BG & !_MC022 &  _MC026 &  _MC030 );
  _X016  = EXP(  BG & !_MC024 &  _MC026 &  _MC030 );

%  |theslave|the_intreq  % 
 _MC028  = DFF(  _EQ023 $  _MC028,  sysclk,  reset,  VCC );
  _EQ023 =  addr21 & !_MC012 &  _MC016 & !_MC018 &  _MC020 &  _MC028
         #  addr21 & !_MC012 &  _MC016 &  _MC018 & !_MC020 & !_MC028;

intreq   = TRI(  _MC029,  _MC028);
 _MC029  = MCELL(  GND $  GND );

%  |themaster|q3  % 
 _MC030  = DFF(  _EQ024 $  _MC030,  sysclk,  reset,  VCC );
  _EQ024 = !BG & !_MC022 & !_MC024 &  _MC026 & !_MC030
         #  BG & !_MC022 &  _MC024 &  _MC030
         #  BG &  _MC022 & !_MC024 &  _MC030;

%  delAS  % 
 delAS   = DFF( !AS $  GND,  sysclk,  VCC,  VCC );
