<<<<< README FILE >>>>> ****************************************************************************** * * * This file has been provided within Allegro because it contains important * * information about this release of software. Please refer to this file for * * information about bug fixes and enhancements, platform issues, and known * * problems. This file contains: * * * ****************************************************************************** o Installation Instruction Notice o Printcap Update Information o Sunview Information o Environment Update Information o Description of this Software Release o Known Bugs o Index of 4.0 Application Alerts o Customer Support Information If you have questions or concerns with this release or have received an incomplete update package please notify Customer Support at 1-800-447-2253. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 INSTALLATION INSTRUCTION NOTICE Please refer to the Allegro Release Notes and Valid's Guide to Operations for any additional information related to software loading and installation procedures. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 PRINTCAP UPDATE You must re-run the "install_printcap" script. Execute the following command and answer the lead-thru questions: % install_printcap Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ENVIRONMENT UPDATE If the pcb_editor should fail to start, check your local environment file for the presence of one of the following lines: source $TELENV or source /usr/valid/tools/pcb/text/env If your local env file is missing one of these lines, please add one of the above. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ALLEGRO IN SUNVIEW Allegro's performance under SUNVIEW has been improved for the 4.0 release. The performance now matches standalone Allegro in cases where the Allegro window is not obscured by other SUNVIEW windows. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 *.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.* * * * * * DESCRIPTION OF THE ALLEGRO 4.0 RELEASE * * * * * *.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.* Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 I. SYSTEM CONFIGURATION This is the Customer Release of Allegro software for Sun workstations. In addition to supporting Sun3's, based on the Motorola 68020 CPU, and Sun4's, based on the Sun4 SPARC CPU, ( Contact your local Valid salesperson for specific Allegro supported model numbers), Allegro 4.0 also supports the new Sun3 workstations based on the Motorola 68030 CPU, and the new Sun4 work- stations based on the Sun 4 SPARC CPU, and the CG6 Graphics Accelerator Board (also known as LEGO). II. OPERATING SYSTEMS Allegro 4.0 requires the Sun UNIX 4.0.3 operating system. The problems known to exist with Sun UNIX 4.0.3 are: o The EDA300/700 graphic interface requires additional software to function correctly. Customer Support will provide assistance to correct this configuration. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 This release of Allegro contains an updated 4.0 symbol library. All library symbols created with previous releases of Allegro are compatible with this software. Before loading the generic library make sure that any customized component symbols are not in /usr/valid/lib/pcb_lib. This library will be overwritten when you load the new Allegro library. Your CAE libraries will not be affected. ---------------------------------------------------- | | | CAUTION | | | | Before using the Valid symbols, carefully | | review them to insure they meet your | | individual design criteria. | | | ---------------------------------------------------- Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 V. DATA COMPATIBILITY WITH PREVIOUS SOFTWARE RELEASES All data created on previous releases of Allegro is compatible with Allegro release 4.0. However, data created/edited on Allegro 4.x IS NOT COMPATIBLE WITH PREVIOUS SOFTWARE RELEASES. Any drawings created or operated on by 4.x software will not function correctly when using 3.X software. We recommend that you always use the latest version of software available. Due to the bug fixes and enhancements that have been incorporated into the 4.0 release, all drawings should be updated. To update your Allegro drawings type: uprevfix Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 Script Compatibility: Allegro scripts created with previous software releases should be updated to make them compatible with Allegro 4.0 functionality Use the following command to update your Allegro scripts: script_convert IV. ALLEGRO/GED IPC HIGHLIGHTING ON SUN PLATFORM ONLY General Description Allegro/GED IPC Highlighting Software: o Performs Show Net in GED and highlights the equivalent in Allegro. o Performs Highlight or Dehighlight Nets in Allegro and highlights or dehighlights in GED. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o Performs Signal Noise Analysis in Allegro and have the analyzed net highlighted in GED. o Performs Place by Reference Designator in Allegro by selecting the part in GED. o Perform Highlight Reference Designator in Allegro by selecting the part in GED. Getting Started: Enter Suntools. Enter the proper schematic directory. In order for the commands to function, you must first establish an association between the schematic and board design. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 It is important to know that backannotation is not required. The fact that we can do "Place or Find by Ref Des" is because when you pick a schematic part, the software is smart enough to figure out the assignment and obtain the corresponding Ref Des on the pcb side. The command to start the process is vtool. Vtool brings up a port which contains Allegro, GED and NameMapper icons. All IPC functionality requires the use of vtool. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ------------------------- FEATURE DESCRIPTIONS ------------------------- GED: Show Net This GED command permits you to specify a signal name and highlights it in both the schematic and board drawing. You can either enter the signal name from the keyboard or select a net with the mouse. Allegro: Signal Noise Analysis If the Highlight field within the Signal Noise Analysis form is set to Network, then every processed signal will be simultaneously highlighted in the schematic and board drawings. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 Note: The schematic page that contains the proper signal must be displayed by GED, or no signal will be highlighted on the schematic. Allegro: Place By Refdes When this command is selected, the user can either enter the Reference Designator in the Allegro port or use the mouse to pick the desired part from the schematic drawing. As the user moves the mouse back into the Allegro port, the proper board symbol will appear in the cursor buffer, ready to be placed. Note: Hierarchical parts are not currently being handled by GED and Allegro. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 Allegro: Hilight Refdes When this command is selected, the user can either enter the Reference Designator in the Allegro port or use the mouse to pick the desired part from the schematic drawing. Both components in the schematic and board drawing will be highlighted if found. Note: Hierarchical parts are currently not handled by GED and Allegro. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ------------------------- KNOWN PROBLEMS ---------------------------- NameMapper is automatically activated when vtool starts up. However, if it could not find the necessary data files (generated by the Packager), it issues warning messages and terminates. This is indicated whenever the NameMapper icon is displayed in the vtool port. User can ignore the warnings at this point. Once an association between the schematic and pcb has been carried out successfully, the user can click the Name Mapper icon again prior to selecting any IPC Highlighting features. One important note about highlighting nets: the proper schematic page must be displayed or the net will not be highlighted. If a highlighted net is not within the display window, GED will automatically center over the "white" color. You must repaint to return to its original color. Hierarchical parts will not highlight between GED and Allegro. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 *.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.* * * * * * * * BUG FIXES & FEATURE ENHANCEMENTS IN ALLEGRO 4.0 * * * * * * * *.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.* Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 There have been bug fixes and feature enhancements in release 4.0. The following list highlights the significant improvements: DRC o Instances of via to via_keepout_all restriction areas that were not being flagged with a DRC marker are now flagged. o When running batch DRC after editing or replacing padstacks, changing DRC rules, or setting properties, only those elements which the changes affect will be checked resulting in a faster, but partial DRC check. o When a null pad is defined on a through hole padstack, the drill hole size will now be used for DRC checking. o Please refer to Allegro Application Alert 4.0-21 for a comprehensive look at the new DRC features. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o DRC violations are now flagged when etch elements on the same net are within the minimum DRC spacing value and would result in manufacturing but not electrical problems, such as when two pads on the same net are too close. To enable same net DRC checking, set the environment variable. Complete instructions can be found in Apps Alert 4.0-21. o You now have the ability to run a "batch drc" in an open drawing within the pcb editor by typing the command: update_drc. This will run a complete DRC check and update the graphic drc violation markers as well as update the batch_drc.log file. In previous versions of Allegro, the batch command "dbfix -d" was only available from a terminal port on non-open drawings. STATUS o When you toggle the line lock parameter while an interactive command is active, the cursor buffer will now immediately update to reflect the current line lock status. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o You can now set a default symbol height for all symbols that do not have heights defined on an individual basis by setting the "symbol height defaults" parameter in the status page. o The status page now has a field that indicates the current state of DRC. It will either read "out of date" or "up to date". When status reads "out of date", you will want to re-run batch DRC before completing your design process. APERTURE EDITOR o The aperture table now displays correct data if you copy aperture stations that do not have D-codes or geometries defined. o The aperture table data is now saved correctly when there are a large number of stations defined in a wheel. o You can now automatically generate an aperture table for any board by selecting the "AUTO" command on the APERTURE WHEEL FORM. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ARTWORK o The photoplot film control form now displays correct data if you open more than one at the same time. o The artwork program can now generate "full contact" thermal relief connections from a pad to a shape on negative film sheets. This feature is enabled by setting the "FULL CONTACT THERMAL" parameter in the photoplot FILM RECORD FORM to YES. o The photoplot.log now informs you if DRC has been cancelled and is not current. If this is the case, you should rerun DRC. It is potentially dangerous to create artworks from a database that contains "out of date" DRC information. o A software fatal error would have occurred if you had several photoplot control forms open, changed the undefined line width parameter without hitting a carriage return, then tried to edit parameters in another of the open photoplot control forms. This is corrected in Allegro 4.0. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o Arcs that were added to the board drawing as part of a symbol are now processed correctly. o Rectangular or oblong pads are now at the correct rotation on artwork films that are generated at 90 or 270 degree rotations. AUTO SILKSCREEN o You now have more control over what symbol subclasses to copy to the autosilkscreen layer. Previously, you only had control over the refdes and the package_outline subclasses. o Auto Silkscreen will no longer move text beyond the board outline. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o Arcs are now always copied to the autosilk subclass. Previously, they would only be copied if they were trimmed because they overlapped a pin or via. DELETE o If you had deleted the last instance of a symbol which had a shape in it, the database corrupted. Allegro 4.0 corrects this problem. DERIVE CONNECTIVITY o There is now a command that allows you to derive a single net. o Derive no longer fails on nets that it began processing at a via instead of at a pin. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o An etch connect that was routed using the same path as another on a different layer is no longer deleted. o Etch lines that failed to be derived are now DRC checked. o Pin escape via connections from surface pads to internal power planes are now being derived correctly. DIMENSION o Auto dimension will now process and add the correct length on odd angle line segments. o The rubber band lines now display correctly if you select 2 points to dimension, select OOPS, and then re-select the second point. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o Dimension lines can now be added without being broken, and the dimension text will be placed above or to the right of the unbroken dimension line. This is done by setting the environment variable pcb_dim_unbroken. Type unset pcb_dim_broken to restore the default mode of adding dimension text within the broken dimension lines. GLOSS o When via eliminate moves connect segments from one layer to another, it will now observe the line width defined in the Net Layer Rule set. o In some cases where grid spacing is non-uniform and utilizes a decimal accuracy greater than 0, the Center Lines Between Pads feature now centers lines correctly. o The Line Entry Into Pads and Center Lines Between Pads features would sometimes run when set to "NO". This has been corrected. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o The Center Lines Between Pads feature now functions correctly on line segments that have vias attached to an end. o When Via Eliminate removed a via at a 3 way (T) junction, the resulting line segment behaved as though the 3 way junction still existed. This problem has been corrected. o Via Eliminate now functions properly if the jog size parameter is set to the default value of -1. o The center lines between pads gloss feature was sometimes creating an undesirable etch pattern where a line would cross back over itself, resembling a bow. This problem is now corrected in 4.0. o The line smoothing feature no longer terminates when it encounters a net containing a dangling end. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 LOAD GERBER o Some lines would be missing when loading gerber files created on Cadnetix systems if there were no tools codes specified in the gerber files. This is now corrected. LOADPLOT o Some filled rectangles would be missing when loading them mirrored. This problem has been corrected in 4.0. MIRROR o The pads on blind/buried vias that were built into a symbol now mirror correctly. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 MOVE o The cursor would be at the wrong location with respect to the symbol being moved if you selected a symbol, moved it, selected OOPS, and then used REJECT to select another symbol. This is now corrected. o The component refdes/symname/devtype information would only appear in the command line if you were moving the last instance of that symbol type. It now appears for all symbols. o The cursor buffer graphics would not display if you selected a symbol, moved it rotated, changed the rotate value, selected another symbol moved it, and then selected OOPS. This problem has been corrected in the 4.0 release. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 NCDRILL o You no longer would get a software fatal error if you selected the PARMS command and no nc_param.txt file is present in the directory(s) defined in the ARTPATH variable. NCTAPE o On Sun4 and Dec 3100 systems, the nctape program would not process and use a correctly formatted nc_tools.txt file. This problem has been corrected. o Nctape now uses any hole size in an nc_tools.txt file even if the hole sizes are not whole numbers. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 NETIN o When performing an incremental add of components and the component device definition is already present in the database, netin will no longer attempt to reference an external device file and it is no longer necessary to have the device file present. o When performing a supercede netin, spare functions defined in the $FUNCTIONS section of the netlist that were not defined in the $NETS section would be removed from the database. This no longer occurs. o Netin no longer recognizes leading and trailing blanks in symbol pin numbers and won't report them as errors when comparing them to the pin numbers defined in the device files. o When performing a supercede netin, shapes would lose their connectivity to elements in the board drawing and have to be manually reconnected. This has been corrected for the release. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 PLACEMENT o User defined "_TOP" subclasses in symbols now mirror to the "_BOTTOM" subclass when placing them mirrored using the automatic or interactive/automatic placement feature. PLOT o Hexagon shape drill figures would be plotted 90 degrees rotated from the way they were displayed. This is corrected in this release. o You can now utilize more than 8 pens when plotting with Calcomp penplotters. o Plots now automatically center if you define a 0 offset and you are trying to plot mirrored. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o There is now an easy to use vers_plot script file that prompts you for all necessary data and plots to Versatec pen plotters. o You would get an error message stating "no stipple file found" when trying to plot with a Versatec pen plotter using the default Allegro environment setup. The environment setup has now been corrected for Versatec plotting. o Circles with a width greater than 0 are no longer plotted as open arcs. o When creating ncdrill drawings, the ncdrill figures/characters would not be added to your plot file unless the ncdrill legend subclass was also displayed. This problem has been corrected. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o The install_printcap program now prompts for and correctly installs Versatec plotters. o In many cases, a number of ncdrill and testprep figures were missing from the ".ipf" plot files. This is corrected in this release. o Drill and testprep figures would not always plot at the same size they were displayed. Figures are now vectorized in the plot file and will always plot at the same size they were displayed when the plot file was created. o The HP and Versatec plotting programs would sometimes terminate before completion of a plot when attempting to draw lines that drew back on themselves, lines that contained very small stepped segments, and lines that contained very small angles. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 RENAME REFDES o There is now an automatic "calculate grid" feature that will generate default grid for running auto RENAME REFDES. o You now have the ability to define characters which should not be used when auto RENAME REFDES assigns new reference designators. REPORTS o On Sun4 systems, a software fatal error no longer occurs when trying to generate the Unconnected Pins report. o The DRC report will now inform you if DRC has been cancelled and is not current. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o There are now two new reports which list ECL net length. They can be invoked using the -v ean and -v eas options in the report program. o The ecl report no longer crashes when processing very large nets. ROUTER o You now have the ability to exclude through hole vias and route with blind/buried vias only by specifying a blind/buried via in the router parameters form. o The router no longer returns a software fatal error if you removed a layer from the routing subclasses parameter form, but left it in the pass5 parameters form. o The router now gets good completion results when routing with a nonuniform grid on a metric board when the routing window had been shifted. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o The router now recognizes the via-line-via parameter in Pass 0. o Insight was selecting multiwire layers as routing subclasses if you chose to allow Insight to routing subclasses. This is now corrected in 4.0. o The router was creating DRC via to text and via to etch rectangle violations when text or etch rectangles were present on nonrouting layers. o The router no longer returns a software fatal error if you do not have Unix file permissions to write a router.log file. o A new router switch, -R, allows the router to add connections with some same net DRC violations in cases where routing results would be worse due to same net DRC checking. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 SET GRIDS o You no longer get a software fatal error if you set a grid such that the X and Y grids are different by a very large multiple of each other. SHAPES o Shapes that overlap are now recognized as a legal connection and the ratsnest will update accordingly. o Autovoid would sometimes add multiple thermal connect lines if you edited a previously voided shape, changed the void size parameters, and ran auto void again. Fixed in 4.0. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o Autovoid would sometimes create a thermal connect line to line/pin/via violation if the width of the thermal connect line was such that the end of the connect extended beyond the void area and within the DRC spacing of a nearby line/pin/via. o When adding a shape, you can now change the active subclass after having selected the Add> SHAPE command. o The ART CHECK command will now always clear all violation markers, including those which fall outside the shape boundary, when the command is rerun. o When the autovoid shape.log is displayed in a port after running autovoid, is is now saved to a file after you select DONE. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 SLIDE o Vias are now moved to the correct location when using incremental keyboard coordinates. o In previous releases, many erroneous drc violation markers would display in the cursor buffer when you selected a connect line having diagonal connections on either end of the connect line you were sliding. This has been corrected for this release. SWAP o A software fatal error no longer occurs if you do not have Unix file permissions to write to the swap.log file. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o Performing an interactive or automatic pin swap would incorrectly recompute the ratsnest of a user scheduled net. The correct ratsnest schedule is now preserved. DISPLAY/DESKTOP o Arcs at width are now displayed at the proper width. Previously, they would be displayed using a 0 width line. o Non-uniform display grid settings now display with the "major" grid points emphasized so that the non-uniform pattern will be more obvious and easier to work with. The "major" grid is the sum total of the minor grids you enter into the Set/Lst> GRIDS form. o The Allegro command menu buttons are now designed to be more consistent with the standard Valid product user interface appearance. The functionality of the buttons has not changed. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o There have been changes that result in a significant performance improvement when running Allegro under Sun Windows. o Rotated padstacks which contained offset pads are now displayed and photoplotted correctly. USER UNITS o Valid has tested 4 decimal place accuracy in metric user units to ensure that all system features operate correctly. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ADDING VIAS o You now have the ability to add stand-alone vias using the Add> CONNECT LINE command. Simply select the command, choose the location for the via, and use the middle mouse popup menu to select DRILL. SET SUBCLASS o You now have the ability to change the name of any user added subclass once it has been added to a board or symbol drawing. Select the "rename" option from the pulldown menu that appears when you pick the box next to a user added subclass in the Set/Lst> SUBCLASSES form, then type the new subclass name. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 NO MOVE o You now have the ability to add a "NO_MOVE" property to components, which prevents interactive editing. (move, delete, rotate, mirror, etc) DISTANCE CALCULATOR o A new feature has been added which automatically computes the linear, manhattan, delta X, and delta Y distances between any two points, as well as the cumulative distance between any number of points. The command can be accessed from any menu page by selecting Set/Lst> DISTANCE CALC. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ADD o If you add a via keepout constraint on subclass ALL, you no longer get a reported database corruption when trying to save the drawing. ADD CONNECT o You no longer receive a software fatal error when auto-finishing a connect if there is no route keepin constraint rectangle in your board drawing. o When creating a T junction, the DRC marker of nearby DRC violations are no longer deleted. o When there is a pad figure on class etch that was loaded by the LOAD GERBER feature, add connection will now perform correctly. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 CHANGE o When changing the subclass of individual line (not connect line) segments and the find filter is set for line segments only, data- base corruptions no longer occur. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 SAVE DRAWING o Upon saving a drawing, Allegro now performs a quick partial consistency dcheck to insure data integrity. If database errors are detected the drawing will be saved with a .SAV extension. DATABASE o In previous releases of Allegro, more than one via could be placed at the same x,y location. Dbcheck will now find this condition and dbfix will remove unconnected vias which fall directly on top of another via. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 *.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.* * * * * * KNOWN BUGS IN ALLEGRO 4.0 * * * * * * This release of Allegro has undergone extensive Alpha * * and Beta feature testing. However, the following is a * * list of known bugs and deficiencies that are still * * present in release 4.0 and will be addressed in * * future releases. * * * *.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.* Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ARTWORK o The aperture file and parameter files may not be saved in the first directory in the ARTPATH if multiple directories are defined and the aperture or parameter file was read from the first directory in the ARTPATH. CURSOR o The cursor may not appear at the correct location when performing interactive commands on drawings larger than C size with 4 decimal accuracy. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 MOVE o User defined net schedules will be removed if you move a component after it has been placed and the schedule has been defined. o When using the stretch etch option, etch may be reconnected to the wrong segments if many overlaps of etch connects occur. SHAPES o The autovoid feature has been enhanced significantly to better handle merging of overlapping shapes and voids. However, at this time the autovoid feature is known to frequently crash and produce incorrect shapes. It is STRONGLY recommended that you make backup copies of any board drawings before attempting to use this feature and that you review any shapes created by the autovoid feature. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 DRC o When using interactive commands or running the update_drc command, the pcb_editor message line count of the total number of DRC violations created/detected will always include any same net drc violations which may be present EVEN if you have this feature disabled with the DRC_no_same_net environment variable. The DRC_no_same_net variable will only prevent same net DRC violations from appearing in the DRC report or from being flagged with a DRC violation marker. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 DERIVE CONNECTIVITY o In some unusual cases, such as when etch doubles back on itself, DERIVE may process the net incorrectly, resulting in an unsuccessful connection, erroneous drc reporting, or erroneous connections that violate Allegro rules. After running DERIVE CONNECTIVITY, you should always run dbcheck to ensure drc is current and no database errors are present. If database errors are reported, manually edit to remove the problem etch or call Valid Customer Support. SIGNAL NOISE ANALYSIS o Signal Noise Analysis is a rapidly evolving product which has been made available in the 4.0 Allegro_Review and Allegro_Engineer configurations as a "BETA" capability. Further improvements, testing and customer feedback are still ongoing. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 *.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.* * * * * * * * INDEX FOR APPLICATION ALERTS * * * * Sun 4.0 * * * * * *.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.* Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ALERT NUMBER 4.0-1: The Network File System (NFS) Overview in the use of NFS to mount remote file systems. ALERT NUMBER 4.0-2: Using Spooler Commands with Allegro Methods for accessing the spooler. ALERT NUMBER 4.0-3: Router Strategy for SMT Strategy to obtain better routing results. ALERT NUMBER 4.0-4: Shifting the Grid When Routing with 8/8 Rules Tips on shifting grids to maximize routing channels. ALERT NUMBER 4.0-5: Using Allegro Derive Connectivity A recommended operating procedure and explanation of limitations. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ALERT NUMBER 4.0-6: User Units and Database Accuracy Explanation of database unit conversion in drawings to avoid roundoff problems. ALERT NUMBER 4.0-7: Using the Edit Shape Boundary Command Tips on editing shape and void boundaries. ALERT NUMBER 4.0-8: Allegro Text Database Conversion Method of using database conversion from SUN to VMS and back. ALERT NUMBER 4.0-9: ThermoSTATS Properties A description of the properties utilized by the Allegro ThermoSTATS program. ALERT NUMBER 4.0-10: Comprehensive Look at Signal Noise Analysis A series of topics discussing various aspects of the Signoise Analysis program. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ALERT NUMBER 4.0-11: Installation of Peripheral Spooling and Automatic Switch Describes installation for Unix spooler and automatic switch on Sun and Decstations. ALERT NUMBER 4.0-12: Modem Installation Describes modem installation of Everex and Telebit on Sun plus Everex on Pmax and Sparcstations. ALERT NUMBER 4.0-13: Using the Net Layer Rule to Control Routing on Layers Describes the Route on Layer feature of the Net Layer Rule Form. ALERT NUMBER 4.0-14: Controlling DRC's Created by the Router Tips on handling the DRCs created by the batch router. ALERT NUMBER 4.0-15: Routing with Multiple Line Widths and DRC Rules Tips on routing a board with many line widths and many DRC rules. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 ALERT NUMBER 4.0-16: 4.0 Gloss Performance Tips on improving your glossing performance. ALERT NUMBER 4.0-17: Allegro's Use of Sun Color Hardware Information pertaining to the color. ALERT NUMBER 4.0-18: Converting 3.x to 4.0 Scripts Explanation of process to convert scripts. ALERT NUMBER 4.0-19: Automatic Aperture Editor Tips on using the new feature that automatically generates aperture files. ALERT NUMBER 4.0-20: 4.0 Acceptance Test Describes the test for verifying basic allegro functionality. ALERT NUMBER 4.0-21: New 4.0 DRC Features Insights into some of the new DRC features introduced with 4.0. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 *.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.* * * * * * * * CUSTOMER SUPPORT INFORMATION * * * * * * * * * *.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.*.* Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 The Customer Support Center Helpline provides guaranteed technical assistance to Valid customers with application, software, hardware and system questions. FEATURES o Special "800" toll-free number provided for single source access to Valid's support organization. o Guaranteed response time. o Well trained industry experienced Application Engineers work with you via the phone. o Coverage from 8:00 am to 5:00 pm local time. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 DESCRIPTION Through a special "800" toll-free number, the Customer Support Response Center records your assigned system ID number and all pertinent information about your problem. The Customer Support Center then dispatches it to the next available Application Engineer if it is deemed to be a software problem and to the appropriate hardware organization if it is deemed to be a hardware problem. You are guaranteed a maximum response time of two hours (2) for software and eight (8) for hardware during regular working hours; normally your questions will be handled immediately depending upon availability of application engineers and the complexity of the problem. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 All your calls are documented and tracked for history analysis. Upon completion of the analysis a Field Support Engineer may be assigned to go on site to work more closely with the customer due to the complexity of their problem or communicating to our engineering staff of the high volume of calls on a particular application that perhaps should be reviewed. The Customer Support Center offers guaranteed response from our most experienced Application Engineers who have the support of the Customer Support department and Valid Engineering. ORDERING INFORMATION For further information, please contact your local Sales Office. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 The Customer Support Center provides a Bulletin Board called VUnet (Valid Users network) which allows the customer to access a variety of information via modem. FEATURES o User area with technical questions and answers posted by customers to each other. o Technical area where Application Notes, workarounds or "Product Alerts" are submitted by our Application Engineers. o News area with information from our Internal Departments ranging from User Group news to Marketing announcements. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 o Course/Class listings with up-to-date class schedules. o Current software version listings. DESCRIPTION A 2400 baud modem is available to the customer with each Maintenance contract. A password and user documentation is sent to each customer after the receipt of the registration form. After a connection, the Valid users have access to technical information posted by other customers and Valid employees. Any information that involves the customers is available on VUnet. ORDERING INFORMATION For further information, please contact your local Sales Office. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 The Customer Support Center has a Tracking Center that allows the customers to report Software Problem Reports (SPR) when they find a software defect, documentation error or an enhancement they would like to see in a future application release. FEATURES o 24 hour response upon receipt of the SPR. o SPR's are tracked by each customer. o Weekly meetings are held to review the open SPR's by our highly technical staff, Engineering and Marketing. o Monthly reports are available upon request. Valid Logic Systems, Inc <<<<< Readme >>>>> 1-800-447-2253 DESCRIPTION The SPR form is received into our Customer Support Tracking Center and logged onto our system. An acknowledgement letter is generated within 24 hours upon receipt of the SPR and sent to the customer. Should an urgent SPR be received, it is immediately hand carried to engineering to start an investigation. If more information is required, a letter is sent requesting the proper data. When an SPR has been reviewed by the proper department, an updated letter is sent describing the recommended action or what actions have been taken. Should the customer wish to review their SPR's, a report will be generated and sent. ORDERING INFORMATION For further information, please contact your local Sales Office. ********** END OF FILE *********