      BUG  FIXES IN ALLEGRO 5.0P2

      The following is a list of bugs present in production releases of Allegro prior to the 5.0 release that have been fixed in Allegro 5.0P2.

      Please note that an SPR number is listed along with each bug. Those bugs which were reported by customers to the Valid Customer Support Center are assigned a 5 digit SPR number, and the customer is notified of the bug number. You can reference this number to determine whether any bugs you reported have been fixed in this release. Bugs reported directly to PCB Engineering by Valid personnel are assigned an internal SPR number with a 2 digit prefix indicating the release it was reported against, in the form XX-XXXX. These bugs are sometimes discovered and reported by Valid AE's as a result of customer inquiries, therefore you should review them in addition to the customer reported bugs.

Add Circle

      40-0494 :  You were allowed to enter a circle whose line width was greater than it's radius. The resulting circle was typically undesirable and could result in artwork problems. You are now prevented from adding such a circle and a warning message will report an error. 

Add Connection

      40-1802 :  When adding a connection with a line width which falls outside the drawing extents, Allegro crashed with a "segmentation fault violation" message. You will now receive an error message and Allegro will not terminate.

      28776, 28877 :  Enhancement requests for the ability to add connections with curves are features of Allegro 5.0P2.

      30-1154, 40-1441 :  A frequent complaint was that the "finish" middle mouse option was accidentally selected, resulting in wasted time while the autorouter routed the connection. This has been corrected by adding an additional level of menu selection that must be made before the autorouter will be invoked. The additional selection that must be made makes it more difficult to accidentally select this option.

Aperture Editor

      40-1780 :  When generating apertures, the default wheel number was always "99". The artwork program would not recognize a wheel number this large. The default wheel number is now number "1".

      40-1122, 40-1590, 40-1742 :  The automatic aperture generation feature would sometimes create duplicate aperture stations and/or fail to create stations. It should now always create a correct aperture table with no missing or duplicate stations.

Artwork

      40-1816 :  Artwork would sometimes create incorrect arcs and circles on films which were created rotated and mirrored using the Gerber 4400 option.

      40-1829 :  When a pad falls within a shape of a different net on a positive film, you would receive an error in the photoplot.log and no pad would be flashed. After receiving several requests to change this, the photoplolog now issues a warning, instead of an error, and a pad will be flashed.

      40-2364 :  Pad shapes in rotated padstacks would sometimes be photoplotted unrotated in the gerber files.

      40-1855 :  Very large shapes would sometimes be photoplotted incorrectly, resulting in the shapes being partially or totally missing in the gerber file.

      30496 :  Lines in a board design were not photoplotted and were missing from the gerber file.

      29272 :  When a design contained pads whose diameter was the same as the width of lines also in the design, and the aperture table contained a single station that was used for both the pad flash and the line draw, an extra erroneous line draw could occur from the last line draw to the first pad flash using the common aperture if the artwork program processed the pads immediately after processing the lines.

      30716 :  Artwork would not place crosshatched shape fill lines in the same location where they were displayed. The crosshatch fill lines will now always display at the same location that they will be placed by artwork in the gerber file.

      30-1098 :  When no aperture existed for rectangular or oblong pads, artwork would fill the pads using the same algorithm it used for processing shapes.  This sometimes resulted in very large gerber files due to the large number of line draws needed to fill the pads. To minimize the size of gerber files when no aperture exists for rectangular or oblong pads, artwork will now search for and use a square aperture equal to the width of a rectangle and a circular aperture equal to the width of an oblong in an attempt to draw rectangular or oblong pads with a single line draw.

      28544 :  When no flash was defined in a padstack for a thermal relief, artwork would flash a matching circular flash on a negative layer if it matched the circular pad geometry defined in the padstack. This effectively resulted in a missing connection from the pin to the shape. Artwork will no longer substitute pad geometry flashes for missing thermal relief flashes.

      50-2033 : A positive shape was incorrectly filled with a large aperture, causing shorts to adjacent pads. This has been corrected in 5.0P2.

Auto Silkscreen

      40-2029 :  Arcs and circles were not always copied to the silkscreen layer, even though they would highlight and appear to be processed along with all other elements. This error is corrected.

Cadnetix Converter

      31140 :  The Cadnetix converter would sometimes create device files which had erroneous "control characters" in them.  The conversion program has been corrected.

      40-2078 :  The Cadnetix converter would always generate soldermask pad sizes that were 10 mils larger than the etch pad size. This can now be controlled using the "-pn" command line option where "n" represents a positive or negative value to oversize the soldermask pad based on the etch pad.

CAE Integration

      29840, 40-2005 :  When running GED2PCB, it would terminate and output errors in the log stating, "T expected" and "illegal segment endpoint".  These problems have been corrected and were related to the netrev program replacing symbols and not correctly reconnecting all associated etch. 

      30221 :  When running GED2PCB, it would terminate and output an error message informing you that "illegal subclasses" have been generated. The board drawing would then be corrupted and you would get a ".SAV" file when saving the design. This error is corrected in 5.0P2.

      31351 :  When PCB2GED was run by multiple users on a single system in the "server mode", typically on a DecStation system, the ownership of the dependency daemon would be updated to that of the first user.  All subsequent users would be unable to successfully run PCB2GED because they would not have permission to update the "deptable.dat" dependency table. This has been corrected so that permissions are correctly set when multiple users access the dependency table when running in this configuration.

      40-0105 :  When running GED2PCB, you would sometimes get an error telling you to "see log", but no log was created. This has been corrected so that you should always get a ged2a.log informing of any error conditions.

      29599, 40-1866 :  A connector in GED that has all of it's pins in the same pin group in the GED chips_prt file would not be swappable in Allegro after running GED2PCB. This was because the pin group was marked as "(1)" and Allegro could not interpret the parenthesis. This problem has now been corrected and Allegro should recognize any text used for pin groups.

      30351 :  When GED2PCB was run on a case where "alpha" was used for a pin group property, the pins would not be swappable in Allegro. This was because Allegro could not interpret the characters used for the pin group properties. Allegro should now recognize any text used for pin groups.

      40-2134 :  When GED2PCB was run on a case where pins were defined as "bidirectional" using the "BIDIRECTIONAL='TRUE'" pinuse property in the "pstchip.dat" file, the property would be ignored by Allegro resulting in incorrect analysis results. This problem has been corrected and Allegro will now recognize this property defined in GED.

      40-1612 :  If, while running GED2PCB, a missing symbol was encountered, you would be informed that a symbol was missing, but you would not be given the symbol name. This has been corrected to provide the names of any missing symbols when running GED2A.

      50-2010 : On the IBM platform, the rpc.associated would not allow updates to deptable.dat, due to ownership conflicts. When a new deptable.dat was created, it was owned by root and not the owner of the filesystem.

Change Drawing Parameters

      29849 :  When changing the drawing extents on a Sun4 or Sparc, Allegro would crash with a software fatal error if you typed the "carriage return" key when the cursor was on the border of the "change drawing parameters" form. This is corrected in 5.0P2.

      12-1049 :  You could not relocate the drawing origin point to a location outside the current drawing extents. 5.0P2 Allegro will shift the drawing extents to compensate for the new origin.

      40-1821 :  When adding another decimal place of accuracy to a drawing, the extents would sometimes change by a factor of 10 because the decimal point would move to the wrong location within the numbers which represented the drawing extents. The drawing extents should now always update correctly when adding or removing decimal places of drawing accuracy.

      28891 :  You could not relocate the drawing origin on a drawing which had drawing units of inches with 4 decimal points of database accuracy that was at least a "C" size or larger. An erroneous message would inform you that the "drawing origin is outside extents...". This is corrected in 5.0P2.

      29430 :  When adding one or more decimal places of database accuracy to a drawing, some shape parameters would incorrectly change by a factor of 10 because the decimal point would move to the wrong location within the numbers which represented the shape parameter values. All shape parameter values should now always update correctly when adding or removing decimal places of drawing accuracy.

Copy

      31029, 40-2367 :  When copying groups of pins, vias, and etch inside a package symbol drawing, the drawing would eventually become corrupt and could not be saved to a ".dra" file. When saved, you would be informed there were errors and a ".SAV" file would be created. This is corrected in 5.0P2.

      30189 :  When trying to copy a group of voids from one location to another within the same shape, you would sometimes get an error message saying, "W- cannot move voids". 

      30-1181 :  We received many requests for a "step and repeat" feature that allowed you to create a pattern of rows and columns when copying one or more items. This new feature has been added to the "copy" command.

Database

      31077 :  Dbcheck would not detect a database error which resulted in a software fatal error crash when running other automatic features. The dbcheck program will now detect this error and other internal database checks have been added to prevent this type of database error from being introduced at all.

      31030 :  Dbcheck would crash with a "core dump" error on a "corrupted" symbol drawing. The dbcheck program will now detect this error condition and report this particular symbol drawing error.

      40-0943 :  Dbcheck would not open a drawing if you entered a drawing path name that began with "../". This is corrected in 5.0P2.

      40-0543 :  Dbfix would not find a board drawing if you provided a board name without specifying the ".brd" extension. This is corrected in 5.0P2.

Set/List Blind/Buried Vias (Define Blind/Buried Vias)

      30458 :  When a blind/buried via was defined that did not contain a pad on either the top or bottom layers, the corresponding top or bottom mask pads would still exist, resulting in the possibility of etch being exposed because an area could be masked where no pad existed. This has been corrected so that all of the mask pads will be made "null" for the top and/or bottom layer if no pad exists.

Set/List Subclass (Define Subclass)

      29659, 30-1061  :  Once a "user added" subclass was added to a board design, it could not be deleted. You now have the ability to delete any "user added" subclass after it has been added, provided there are no elements on it.

      40-0505 :  When a subclass was changed to or from an etch layer to a multiwire or microwire layer, drc was not automatically run.

      31027 :  When a symbol was added to a board design, and the symbol contained elements on a "user added" etch layer which was not yet added to the board design, the "user added" etch layers would sometimes be added to the board in an order different than the order of etch layers in the symbol. This has been corrected by preventing you from adding any symbol which contains elements on an etch layer not already defined in the board design. 

      40-1470 :  When adding a padstack to a symbol or a symbol to a board, Allegro would search the directory defined by the "PSMPATH" environment variable to find any pad shape symbols defined in a padstack. This has been changed after receiving requests that Allegro search the directory defined by the "PADPATH" environment variable.

Delete

      40-1651 :  You did not have the ability to use the "delete>cut" feature to cut out sections from an arc. You can now use this feature to cut sections from within an arc.

Dielectric Generation

      40-2152 :  The automatic dielectric generation feature would fail to generate dielectric "patches" for conductors which ran under bonding wires. This is corrected on 5.0P2.

Display

      29936, 40-2136 :  When a color was turned off using the "color priority" form, any nets highlighted with that color also became invisible. Highlighted colors will now remain visible.

      40-1151 :  There were many requests for Allegro to display the current color for etch subclasses during interactive etch operations. The ministatus now has a color box next to the current active subclass and a "visibility" form showing all etch colors and visibility during the "add connection" command.

      31496, 31257 :  When moving or mirroring SMD symbols, where the layers for defined pads are visible, pad outlines were not displayed in the dynamic cursor buffer while moving the symbols. Those pads  will now display in the dynamic cursor buffer.

     50-1330 : Graphic redisplays became corrupted when using cancel after executing Signal Noise Analysis. The display problems forced the user to exit the Allegro editor. This is no longer a problem.
     
Distance Calculator (Measure)

      30220 :  When selecting a rectangle, Allegro would crash with a software fatal error or it would hang and have to be manually terminated. This problem has been corrected and you can now select rectangles as points to measure.

Drafting

      30-1348 :  When selecting an element to be automatically dimensioned, the element would not highlight to indicate it had been selected. This is corrected in 5.0P2.

      28771, 28777, 40-1645 :  Customers requested drafting and dimensioning feature enhancements to give more control over the format and units of dimension text, arrow sizes and styles, etc. The drafting and dimensioning features in Allegro 5.0 have been enhanced to include these and many more user controls.

DRC

      40-2399 :  Where a vertical etch connect was in drc violation to 2 horizontal etch segments connecting to a parallel vertical segment, only one drc marker would be generated. Even though it is impossible to correct one of these violations without correcting the other, the DRC feature has been changed so that it will flag 2 violations instead of one.

      29486 :  No drc violation would be detected when one symbol fell directly on top of another symbol that had the same symbol outline. This has been corrected so that a drc will now be issued.

      40-1698 :  When performing interactive operations that resulted in same net drc violations, the message line would give you a count of drc errors which included same net drc errors even if the "same net drc" feature was disabled. The count of drc violations in the message line during interactive operations is now always correct based on whether "same net drc" checking is enabled or not.

      30222, 30569 :  When "same net drc" checking was enabled, it would erroneously flag etch segment to pad violations if the etch "bend point" fell within the pad area. "Same net drc" should no longer flag these instances as violations. It should now consider the first segment which actually exits the pad area as the "connecting" segment regardless of whether or not one of it's end points originates from the origin of the pin. 

      28391, 30-1440, 40-1327, 40-1404, 40-1531,  40-2158 :  When a via or pin was moved within a shape that would eventually be photoplotted as a positive layer, no drc violation was flagged even though artwork would report this as a "short". You can now define etch layers as "positive" or "negative" on the "define>subclass" form for drc purposes, and drc will check for and flag violations correctly based on the intended artwork film type.

      40-1838 : No violation would be flagged between a pad that fell partially within a shape and a nearby connect line because drc used the antipad size, which was smaller than the pad size, to check from the line to the pad. DRC made this incorrect assumption because it always checked pads within shapes as though they would be flashed on a negative layer. In release 5.0, DRC will flag this error because it now checks pad sizes based on the artwork film type switch set by the user.  

      30223 :  When a via having a pad defined on only the top layer is used as a "test via" in "test prep", drc would flag an erroneous "top via" to "bottom pad" drc violation from the via to an SMD pin defined only on the bottom layer. This is corrected in 5.0P2.

      31394 :  When a text size was modified using the "define>text" command and text on class etch became larger, no automatic drc check would be initiated upon completion of the command. This resulted in undetected drc violations until a batch drc was invoked. This has now been corrected so that a batch drc will be automatically invoked.

Edit Text

      31585 :  Allegro would crash with a software fatal error when an attempt was made to edit an empty text node created by the SciCards Conversion program. This was a problem with "edit text", and not with sci_in, that has been corrected so that you can now edit the text.

      30004 :  It appeared as though you could not delete the first "/" character in an NC Drill legend header by moving the cursor one space to the right of it and then pressing the "delete" key. This problem was related to the fact that the second character in the string was a "space", and it has now been fixed.

Edit Vertex

      29788 :  When editing the off-grid vertex of any element and attempting to move it incrementally by typing the "ix" and/or "iy" commands, the vertex would always snap to the grid point nearest the coordinate typed. This has been corrected so that the vertex will move the exact distance typed, and it will no longer snap the vertex to a grid point.

Genrad Interface

      30002 :  When defining an input tolerance, the user documentation instructed you to input a value using the syntax: "n%". When the interface was run, it created an output file and added an additional "%" character to those places where you had already put one, as you were instructed to by the documentation. The Genrad interface will now check to see if you have already provided the "%" character, and will not add it if you have already done so.

Glossing

      40-1832 :  Line Entry Into Pad glossing would not gloss some instances and the log would not report any reason for the failures. 

      40-1831 :  Automatic filleting would not fillet instances where the first vertex in a connection exiting a pad fell within the pad area. It has been enhanced so that it will now process instances where the first vertex of a connection falls with the pad area.

      40-1783 :  Customers had requested that the existing fillet functionality in Allegro 4.1 be enhanced to provide more user control and flexibility.  Allegro 5.0 adds the ability to fillet pins or vias only, to avoid filleting pins without drills, to define a maximum pad size for filleting, and to define a maximum line width for filleting.

      31611 :  When automatic filleting was run on a board having a drc violation from a connect line segment to an adjacent pin, the violation marker was removed and not re-added when that particular line segment was filleted. The drc marker would return only when a batch drc was run or when the connect line segment in question was modified. Automatic Filleting has been corrected so that it always re-adds the drc violation marker when it processes any connect segment which contributes to a drc violation. 

      40-1152 :  This SPR is a request for a "widen trace" feature. The Allegro 5.0 new glossing feature called "Line Fattening" responds to this.

      29770 :  Via Eliminate glossing would crash and return a "fatal error = 11" message when run on a case where connections began at a via on one net and ended on, but did not connect to, connect lines of a different net. Although this is an unusual condition, Via Eliminate has been fixed to no longer crash when it encounters this condition.

Set/List Element

      30649 :  When using list element to select a package symbol, it was necessary to pick on a symbol pin in order to find the symbol. Selecting the outline did not work. This problem with the Allegro "find processor" has been corrected and you can select any part of the symbol to "find" it.

      40-2094 :  When selecting ecl nets, an incorrect "net path length" was reported. This problem was due to an incorrect computation in measuring the net length and has been corrected. 

Mirror

      31033 :  When performing a "mirror by window" of many components, they would be placed slightly off the grid location intended.  This is corrected in 5.0P2.

      29747 :  When performing a "mirror by window" of many components, pads were not placed in the correct locations for their symbols. Pads will now be located correctly.

Move

      29358 :  After running glossing on a board, any attempt to move a particular reference designator would result in the following error message: "illegal drc dbptr error". This false error condition has been eliminated.

      30-0447, 40-1455 :  The move command with the "stretch etch" ministatus option turned on would not operate the same way with vias as it would with symbols. This has been enhanced so that you can move vias and stretch etch exactly the same way that it does with symbols.

      28826 :  When attempting to move a symbol having three or more connections to a single pin with the "stretch etch" ministatus option turned on, only one of the three connections would stretch. This has been corrected so that all connections on all pins of a symbol will stretch properly.

      29672 :  When a shape was active and being edited, the move command would allow only voids associated with the active shape to move. The move command has been enhanced to move the same elements that can be moved when a shape is not active.

      50-1932 : The message "extents outside drawing" could occur when rotating symbols in the move command. The extents are now calculated correctly during rotate symbol.

Multiwire Interface

      31618 :  On a partially routed board, the "fromto" file created did not list correctly the instances where SMD pin escapes were being shared by more than one component pin. This is now reported correctly.

      31451 :  The multiwire program would terminate with no error message when reading a multiwire file that contains a wire segment that falls directly on top of another segment. This condition is nonstandard, and not typically generated by the multiwire routing program. The Allegro multiwire interface has been enhanced so that it will no longer terminate when it encounters this condition. However, it will reject the segment and will not read it into the Allegro board drawing.

      28768 :  On SMD boards that contained pin escapes manually added to symbols in a board drawing, the "fromto" file created would reference the SMD pins and not the manual pin escapes. This has been corrected so that manually added pin escapes are recognized and listed in the "fromto" file.

      50-2041 : The multiwire interface would core dump when the command file included "fromtoall". This has been corrected in 5.0P2

      50-2032 : The from-to list extracted from Multiwire did not match the user defined schedule withing Allegro. This has been corrected in 5.0P2 

      31774 : Route keepout areas which were part of a symbol were being ignored in the Multiwire interface. This enhancement request has been added to 5.0P2.

      31770 : The Multiwire interface would core dump when reading data created by the DWIRS program f2gen. This has been corrected in 5.0P2.

      31773 : The Multiwire interface did not recognize certain keywords created by the DWIRS system. Invalid error messages will not be printed in the log file in 5.0P2.

NC Drill

      30219 :  A pin on a symbol that had been copied would not issue an ncdrill figure and would not be added into the ncdrill legend. This has been corrected so that all pins with the correct pin visibility should issue an ncdrill figure and be added into the ncdrill legend.

NC Tape

      30431, 40-2220 :  The last drill would be missing from the ncdrill.tap file when the "repeat codes" parameter was set to yes. This has been corrected so that the "repeat codes" parameter no longer causes a missing drill.

      40-2351 :  On DecStation systems only, nctape run on a board would create some erroneous holes in the ncdrill.tap file. This DecStation only problem has been corrected so that nctape runs exactly as it does on all other hardware platforms.

      29789 :  On a very large board, the order of the via drills was not optimized properly even though the "optimize drills" parameter had been set to "yes". This has been corrected so that the number of drills processed has no effect on the optimization feature within nc tape.

      31686 :  When an offset was specified in the ncdrill parameters file, some drill locations were incorrect in the ncdrill.tap file. This problem was related to numeric roundoff in drill location calculations, and it has been corrected so that a drill offset does not affect the accuracy of the drill locations.

      50-2036 : When running nc_tape with modified parameters, nc_tape would not read the changed nc_param.txt file and would use only defaults.

Netin

      30076 :  When attempting to perform a "syntax check" only on a netlist file containing only a user defined schedule for a net, a syntax error would be reported even though netin would run successfully when not run in "syntax check only" mode. This problem with the "syntax check" feature in netin has been corrected so that it properly checks netlist files containing user defined schedules.

      29432 :  When running netin using a netlist created on FutureNet in the "supersede" mode with the "rip up etch" parameter set to "yes", existing etch on originally unnamed nets would sometimes be "ripped up". This occurred when the nets were "renamed" during netin. This has now been corrected so that unnamed nets, those with the "TN-" prefix, are first checked to prevent them from being renamed if possible. 

Padstacks

      40-2365 :  Padstacks which contained drill holes offset by a negative value would not be correct when added to a board design. The hole offset values would be different than those originally defined in the padstack. The negative offset value will now be processed correctly.

      40-1909 :  When attempting to save an SMD padstack having only a pad defined on the top layer, an erroneous warning message informed  you that an ncdrill hole was required for padstacks containing a top pad. This warning message was erroneous and is no longer issued when creating SMD padstacks.
 
      30224 :  After editing a board padstack, a board drawing was corrupted and could not be saved as a ".brd" file. The check that occurs during "save" would find an error and save the board drawing as a ".SAV" file.  This is corrected in 5.0P2.

      30-0768 :  Allegro would not allow you to define a "null" pad for any subclass on a through hole padstack. The padstack editor would always default these to a round pad equal to the size of the drill. Allegro will now allow you to create "null" pads on through hole padstacks.

      30-1096 :  You did not have the ability to replace a padstack in any of the symbol editor drawings. The padstack editor has been added to the package and mechanical symbol editors.

      30-0341 :  When a new board drawing was opened and no "via.pad" padstack was found in the current "PADPATH" environment variable directory path, an error message would inform you, "error opening file." This error message has been changed to: "Couldn't find padstack: No match found for via.pad in the search path."

Parallelism

      31026 :  When the "parallel" command was run on a board where 2 etch segments were perfectly parallel to each other on adjacent layers, no error would be reported. This has been corrected so that the parallelism feature recognizes and reports these errors.

Placement

      30077 :  Automatic placement would not place components on the bottom side of a board when a package keepout area was defined only on the top of the board. This drc checking problem has been corrected to check symbols correctly for top and bottom package keepouts.

      40-2013 :  When automatic placement was run on a particular case, it would return a message saying, "no available buffer ids" and eventually crash with a software fatal error. This was identified as a problem that would occur only when running automatic placement in the "interactive" mode, and it  has been corrected.

      30225, 40-1959 : The "plctxt" program has been enhanced to support "alternate symbols".

      40-1732 :  When the "plctxt" program encountered an error, it terminated and did not list details of the error in the log file it creates. This has been corrected so that the log file will now contain the name of the last successfully added component and the component which caused the error condition.

Plotting - Versatec

      31541 :  Very small and very large arcs would sometimes plot as complete circles. This problem has been corrected and all arcs should now plot correctly.

      29701 :  When plotting a board outline, some odd angle lines would not be plotted at all. A problem with plotting odd angle lines was discovered and corrected and they should now plot correctly.

Plotting - HP

      31108 :  Some arcs on a particular case would plot with an erroneous extra line draw between the end points of the arcs. This problem has been corrected and arcs should plot correctly.

      30359 :  When the -F1 (use plot hardware text option) switch was specified, some text blocks would plot such that the text characters overlap each other. A general problem was discovered and fixed to correct this wherever the text spacing is equal to or greater than the pen width. This fix does NOT address situations where the pen width is larger than the text spacing.

      40-2146 :  When running the hp_plot script or the plot_ipf command, the last line of the .plt file being plotted would echo to the console. This has been corrected to echo the version of the plotting software.

Redac Converter

      40-2121 :  On a particular case, the redac_in converter would create an incorrect "autobrd.scr" script which would terminate after netin was run This error is corrected and the script should run to completion.

      40-2099 :  The redac_in converter would create an Allegro board drawing which had "stacked via" violations where vias were placed directly on top of each other because they existed this way in the redac design. This has been corrected so that multiple vias will not be placed directly on top of each other in Allegro.

      40-1896 :  When converting a redac "split board", the vias from one half of the redac design would not would not be converted to the Allegro database created. This has been corrected so that all vias from a redac "split board" design are now converted correctly.

Reftxt

      31485 :  When the reftxt program was run, it would not update the state of the board in the dependency table at all. The reftxt program has been corrected so that it recognizes a board having a CAE dependency and it will update the dependency table properly.

Reports

      30-0622 :  All reports received a default extension of ".txt". This has been changed to give reports a default extension of ".rpt", making it easier to sort them from other text files.

      30244 :  The drc report would erroneously flag a delay rule net violation on a particular case. This problem was identified as a computation error in the net manhattan length based on the timing delay information provided. The net length is now computed correctly based on timing delay data.

      30046 :  When the ECL report was run on a case where the ecl property existed on single pin nets, the reports program would hang in an endless loop. The report program will not hang when single pin ecl nets exist in the design.

      40-1881 :  The format of the ecl report was difficult to read when net names exceeded 19 characters. This has been corrected by putting long net names on a separate line.

Rotate (Spin)

      20-1636, 20-1711 :  Requests asked for a rotate command which does not force a move of the symbol when rotating it and specifies an "absolute" rather than an "incremental" rotation value. The new spin command performs this task.

Router

      30529 :  The router would ignore very small router keepout areas, less than one router grid in size, that were being used to prevent the router from putting in connections between pins. This has been corrected so that router keepout areas do not have to be a minimum of one router grid unit.

      30-1216, 40-1515 :  On cases where an offgrid rectangle was used to force the router to route between the pins of an off grid component, the router would still not route between the component pins even though there was a legal open channel. This has been corrected by implementing an improved slide feature within the router which does not require an offgrid rectangle to route between offgrid pins.

      40-1082 :  The router would sometimes violate the "side entry allowed" parameter if it was set to "no" and add a pin escape to an SMD pin that entered the SMD pin from it's long side. Now the router will always properly observe the "side entry allowed" parameter.

      40-1483, 40-1641 :  The router would always select the most conservative set of drc rules from all of the drc rules set on all nets and all layers, resulting in ineffective routing when different drc rules were set for different layers and/or different nets. The router has been improved to always use the appropriate drc rules for all nets and on each layer as it is routing. 

      40-1735 :  On a particular case where offset vias were allowed, the router would only offset the vias in the "Y" directions, resulting in inefficient overall routing results. This problem has been corrected and vias will now also offset in the "X" direction.

SciCards Converter

      31588 :  When converting a Scicards design, the tilde character "~" was not being interpreted resulting in an incomplete conversion. This has been corrected and the tilde is now interpreted as the user's home directory.

      31583 :  When converting a particular Scicards design, text strings containing only one character in the Scicards design were being converted to empty text strings in Allegro. This problem has been corrected and all text strings should now convert properly.

      31582 :  When converting a particular Scicards design, SMD padstacks on bottom mounted components in the Scicards design were not being created correctly in Allegro. This problem has been corrected and all SMD bottom mounted components should now be properly converted to mirrored components in Allegro.

      31581 :  When converting a particular Scicards design, etch text on the bottom of a Scicards design was not being created correctly in Allegro. The problem has been corrected and all etch text should now be properly converted to mirrored text in Allegro.

      31580 :  When converting a particular Scicards design, incorrect Allegro scripts are created that fail to run successfully. The problem was identified as incorrectly adding quotes around board symbol names, resulting in a script failure. This problem has now been corrected.

      31577 :  When converting a particular Scicards design, the script created stops executing and prompts the user for a subclass name, forcing a situation that would likely lead to an error. This was a problem in creating the script and has been corrected.

Scripts

      31224 :  When recording a script that utilized stickup prompts for "X" and "Y" keyboard coordinate entries, replay of that script would produce an error. Keyboard entries are now correctly recorded.

      30577, 40-2306 :  When attempting to replay a script containing references to user added subclasses, the script would fail on any board not having the all of the exact same user added subclasses in exactly the same order. Scripts are enhanced so that subclass names are stored in scripts which allow scripts created from one board to be played in any design.

      29179 :  When a script was recorded that added a refdes label text to more than one subclass in a symbol drawing, the script would not replay. This was a problem with scripts replaying the "label>refdes" command that has now been corrected.

Set/List Properties (Define Properties)

      29360, 30-0816 :  When the ecl property was added to a net that had the no_rat property set, the no_rat property would be automatically deleted.  Adding the ecl property will no longer delete the no_rat property.

Shapes

      40-1941 :  This SPR is an enhancement request for the ability to add shapes on classes other than etch. Add shapes is now permitted on almost all classes.

      40-2520 :  When editing the boundary of a shape on one layer, voids on any visible shape on another layer would be deleted if they fell within the area of the new shape boundary created. Editing the boundary of a shape will now modify only the shape being edited.

      40-2004 :  Allegro would not recognize more than 32,767 pins on a net within a shape, resulting in incorrect flashes in the artwork gerber file. This problem has been corrected to allow an unlimited number of pin connects within a shape.

      28838, 28858, 20-1691, 30-1347, 40-1674 :  These SPR's request the ability to add nonrectangular keepin and keepout constraints. Allegro now allows you to add shapes on keepin and keepout class/subclasses, and it will recognize those shapes as constraint areas.

      30556 :  When GED2PCB was run on a board with many complex shapes, it appeared to hang indefinitely and had to be manually killed. When an attempt was made to manually delete the shapes it also appeared to hang.  Enhancements have been made to make the DRC and connectivity checking for shapes more efficient, thus improving the performance of shape operations.

Signal Noise Analysis

      29488 :  This SPR is an enhancement request for signoise to read an existing report file without recomputing all analysis values.  Signoise will now read the "net file" and "report file" specified in the Signoise parameter form if either of them are enabled.

Slide

      29702 :  On a particular case, slide would hang in an infinite loop when it attempts to bubble etch around a via to avoid a drc violation. This problem has been corrected and slide should now bubble etch correctly.

      30719 :  On a particular case, an unflagged drc violation would be created when interactively sliding a cline and via on top of another via. The drc violation would not be flagged with a drc marker until either a batch drc was run or until the etch and/or vias were modified using another command.  This problem within the slide command has been corrected and drc violations should be flagged properly.

      30-1049, 40-2009 :  These SPR's are enhancement requests for the ability to slide etch and automatically bubble per the drc spacing rule instead of the current grid. The via bubble feature within the slide command now provides this functionality.

Test Prep

      30639 :  Test prep would crash with a software fatal error when run with the "test unused pins" parameter set to "on". This problem has been corrected and test prep should operate correctly using this parameter.

      30545 :  When a particular board was run on a Sun3, all of the test probe text would be incorrectly placed on the left side of the board. This problem has been corrected and test prep should operate correctly on a Sun3.

      30522 :  Test prep would crash with a software fatal error when run with  the "allow auto test pad insertion" parameter set to "on". This problem has been corrected and test prep should now operate correctly using this parameter.

      40-0466 :  This is an Enhancement request for a property to control nets processed by test prep. There is now a "no_test" property which will prevent nets from being processed by test prep.

Thermal Analysis

      30459 :  When spaces were present in device names, thermal analysis would not process them correctly and report an error saying, "Input garbled".  This problem has been corrected and thermal analysis will now correctly process devices containing spaces in their names.

VT100

      40-2293 :  When running glossing in the background, a new vt100 terminal could not be opened. This is corrected in 5.0P2.


    5.0 BETA BUGS FIXED IN RELEASE 5.0P2

      The following is a list of bugs that were present in Beta versions of Allegro 5.0 and have been fixed in Allegro 5.0P2. These bug fixes are only of interest to those customers who performed beta testing of Allegro 5.0B1, B2, and B3.

Add Connection

      The add_connect Ministatus parameters would return to the default values and were not saved once you exited the add_connect command.  Any values you enter into the add connect ministatus parameters are now saved correctly when you exit (not cancel) the add connect command.

Add Symbol

      When placing a symbol containing a filled rectangle at an odd rotation, the filled rectangle would not be added at the correct angle relative to the way it was originally added to the symbol. Filled rectangles in symbols are now always added at the correct rotation when you add symbols.

Add Rectangle

      When adding a filled rectangle and changing the active class/subclass to one of the keepin or keepout classes, a batch drc would not automatically be invoked and the status form would report that DRC is out of date.  Adding new keepins and/or keepouts initiates a DRC check.

Add Pin

      You could not add a pin containing a pad shape to a symbol drawing having user units of millimeters and a decimal accuracy of 4. A message would tell you "pin outside drawing extents". This is corrected in 5.0P2.

Add Shape

      When adding shapes on any keepin class, they are added as unfilled shapes and you are not allowed to add voids. When adding shapes on any "keepout" class, they are added as filled shapes and you are not allowed to add voids. All other shapes are added as filled shapes and you are allowed to add voids. In previous beta releases of 5.0, shapes on other than keepin, keepout, or etch subclasses could be added as either filled or unfilled.

Alternate Highlighting

      If you ran Allegro from within Sunview in OS 4.1 or 4.1.1, you would experience damaged graphics and eventually a software fatal error crash when using the Alternate Highlighting "dashed font." This problem is a Sun OS bug and has been addressed by disabling the "dashed font" capability when running Allegro under SunView or in standalone mode. The problem does not occur when running under Sun OpenWindows or under Xwindows. In 5.0B1, you could disable the "dashed font" by setting an environment variable called "bug_nohilitefont".  In 5.0B2 & 5.0P2, the "dashed font" is disabled by default and, if Sun releases an OS patch which fixes this bug, the "dashed font" can be enabled in Allegro by setting the environment variable "enable_hilitefont".

Artwork

      Some arcs in mirrored film sheets would be slightly incorrect.  They are now correct for 5.0P2.

      The "suppress unconnected pads" option would work exactly opposite of its setting. It is corrected in 5.0P2.

      Some rotated rectangular pads would not be filled correctly when the fill lines were added by artwork. Rotated rectangular pads fill correctly in 5.0P2.

      Some shapes, which contained very small "jogs" or "steps", would not be filled correctly where the "jog" or "step" occurred. The shape border fill lines would pass by them as though they did not exist. These are now correctly profiled.

      Some rotated rectangles were being deleted from artwork files, where a message in the photoplot log reported the rectangle outside the plotting window.

Define BBVia

      Sometimes a message saying "record out of buffer limits" is issued when trying to define a new blind/buried via. This error is corrected in 5.0P2.

Change Drawing Parameters

      When adding an extra decimal place of accuracy to an existing drawing, all ncdrill hole sizes would be updated incorrectly. They now update correctly.
  
Copy

      Sometimes a software fatal error crash would occur when copying a pin in a package symbol drawing when the ministatus was set to polar mode with the angle set to "90" and the copy origin set to "user pick". Allegro 5.0 corrects this error.

      The "row" and "column" labels in the ministatus were reversed so that when you entered a "row" value, you were actually entering a "column" value. This has been corrected in 5.0P2.

Desktop

      There is now a "drawing mode" parameter in the new drawing parameters and change drawing parameters forms which indicates what kind of drawing (layout, package symbol, mech symbol, etc...) is active. Some commands and ministatus class/subclass settings will now be restricted so that they are not available unless you are working in the correct "drawing mode". 

      The global "set all colors" box has been removed from the colors subclass form as a result of many complaints about accidental picks.

      The "copy" command in the file manager port would not work. You would get a message telling you that the "feature is not supported yet".

DRC

      Batch DRC would not flag any text on an etch subclass that fell within a route keepout constraint. Text is now flagged.

      No DRC violation would be flagged if an etch shape fell partially outside of a route keepin constraint. Shapes are now correctly flagged.

Drafting

      There was no "find filter" available when selecting elements using any of the drafting or dimensioning commands. You had to use "reject" to find elements other than those initially selected. A find filter has now been added to make it easier to select elements.

      You would sometimes get a software fatal error when selecting a group of elements to datum dimension all at once.

Edit Vertex

      In Allegro 5.0B1 you could not edit vertex of any filled rectangle. This problem has been corrected and you can now edit vertex on filled rectangles.

      Edit vertex of a shape boundary would not perform shape boundary checking correctly and sometimes allow you to create an illegal shape whose boundary overlapped itself.

Evaluator

      The histograms are now scaled such that you have a common reference for comparing the X axis histogram against the Y axis histogram.  

      When run, the evaluator now selects colors beginning with the lowest priority colors so that you can view symbols and etch on top of the evaluator maps.  

Gloss

      Line fattening gloss will now fatten lines beyond any route_line width property set.

      Auto Fillet glossing would sometimes remove a drc violation flag on a cline segment it glossed if that cline segment were in violation to a nearby pin. The DRC flag is correctly displayed.

      Line and Via Cleanup, Line Smoothing, Line Fattening, and Pad Filleting would not work when used in the "by highlight" mode.  

Insight

      Insight would not reselect the "typical thru" and "typical smd" pins when it was rerun on a board.

      Insight would not enable the delay rule router on boards that had the delay rule property set on nets.

Interactive Commands

      The Oops pop-up option did not operate correctly in interactive commands when you selected elements by window or by group. This problem has been corrected and the oops pop-up option should now function correctly when using interactive commands by window or group.

      You would have difficulty selecting pins that have offset pads when making a mouse pick directly on them. This problem has been corrected and you can now select directly on or close to pins having offset pads to "find" them.

      The move, copy, and spin commands would not work correctly when operating on a symbol relative to its body center. Body centers are now calculated correctly and all interactive commands which allow you to operate on a body center should work correctly.

      The mirror command would not operate correctly on some symbols that were placed at odd rotations. This problem has been corrected and the mirror command should now operate correctly on all rotated symbols.

Move

      You are now given an information message telling you when you would be moving a symbol pin, creating a non-standard (exploded) instance of the particular symbol.

Multiwire

      When generating a multiwire file, instances where a single pin escape was used for more than one pin on a net were sometimes not being handled correctly in the output file.

NC Drill

      The "suppress zeros" parameter was working exactly opposite of the value you set it to in the parameters form.

      A new parameter has been added to the parameters form which allows you to specify that equal coordinates, from one line specifying a drill location to the next, should be suppressed.

Placement

      You would get a software fatal error when autoplacing a component that had pins on the same nets as unplaced components having "dense component" properties on them.

Plotting

      Offset pads would sometimes be plotted incorrectly when the plot file was created from a drawing having user units of millimeters and a decimal accuracy of 3.

      Plotting of very small or very large arcs on versatec would sometimes plot them as complete circles.

      Pads as shapes would always plot hollow, regardless of the pad fill style selected. 

      An "auto clipping" parameter has been added to plot_ipf and hp_plot which will force elements to be plotted only to the extents they were visible in the display window when the plot file was created.

      Vp_plot was not creating the spooled output file when some artwork data was converted using gbplot. This was caused by incorrect size calculations for some rotated rectangles.

Reports

      The placed and unplaced reports would sometimes fail and return a system error when run.  

Router

      The Pattern Router would not observe the Route by Room or Route by Window constraints. It now recognizes these constraints and routes properly within them.

Sci_in

      The sci_in conversion program would fail when you used a tilde character to represent your home directory in the input argument.

Shapes

      There is no longer a 64,000 edge limit within a single shape. This limit might have been encountered when autovoiding very large, complex shapes.

Test Prep

      The command for adding a test probe keepout area was called "test keepout".  It has been changed and is now called "probe keepout".

Tune_pcb

      When running the tune_pcb program on a remote X terminal, the program would crash with a segmentation violation.

Show Parasitics

      The capacitance between two nets would sometimes be computed incorrectly based on the order in which you selected the two nets.
