 5.0 Analysis Tutorial - High speed technology problems (*** scroll ->

As design technologies increase in speed, it is obvious 
that timing concerns increase. Engineers focus on 
their design's critical timing paths. As component speeds
increase without always scaling down board sizes there is
an increase in the relative importance of the interconnect 
propagation time (time to travel the connection length)
and settling time (time to settle down of ringing of 
reflections from stubs, etc ).

Less obvious is the fact that the magnitude and need for
concern over crosstalk also increases in direct proportion 
to the speed of the design technology.

For the same nets and layout which we just showed to 
be noise free for slow TTL technology we now substitute
models for a faster ASTTL technology. THE PLACEMENTS AND
ETCH ARE EXACTLY THE SAME AS before.  We have simply
forced analysis to assume much faster components by
editing the elecmodel.dat file. The elecmodel.dat we are now
using has the following contents: (lines beginning with # are comments):

 # ( Electrical models for driver and receiver pins )
 # Source: TI AS/ALS Logic Data Book 1986 pg. 4-19,20
 MODELNAME TI_ASTTL
 DEVMATCH=*
 VOLTAGE_IN_LO=0v,0.8v
 VOLTAGE_IN_HI=2v,5v
 VOLTAGE_OUT_LO=0v,0.4v
 VOLTAGE_OUT_HI=2.7v,5v
 REFTEMP=25
 TEMPCO_LO=0mV/degC,0.6mV/degC
 TEMPCO_HI=1.2mV,1.5mV
 RCVRCAP=5pF
 RISETIME=1.7nS
 FALLTIME=1.2nS
 DRVRIMPED_LO=10ohm
 DRVRIMPED_HI=34ohm
 
 # The "DEVMATCH=*" above forces everything to ASTTL, 
 # For reference the TTL alternatives would be approx:
 # RISE/FALL=12/8ns,RCVRCAP=3pf,DRVIMPED_LO/HI=20/50ohm


Note that the
predicted ASTTL noise values are much larger than they were
for the equivalent TTL design. For example
for the net BUSCTRLL10 shown:

                BEFORE(TTL)    NOW(ASTTL)
                -----------   ----------
 Back Xtalk:    ~ 330mV        ~ 2300 mV *
 Forw Xtalk:    ~   9mV        ~   60 mV
 Overshoot:     ~  14mV        ~  860 mV *

 violations with negative noise margins and excessively large 
individual noise ingredients are flagged with "*"'s
in the "Delay and Distortion" report window.
 
 Middle button click the Param softkey (left edge of screen)
 to view the current user defined settings of noise and
 timing threshold rules.  Also note how for speed of
 demonstration a select list of nets and previous saved
 report of data are being viewed.  Complete analysis of
 these 24 nets takes several minutes. Once the data has
 been collected it can quickly be perused using the
 "First, Prev, and Next" buttons.  
 
 You should "DONE" the parameter window and you might want
 to middle button pulldown on the border of this help window to
 "back" then "front" this help window to better view the layout
 and the highlighting of the current net being analyzed.

 ****************************************************
 Hold down the middle button over the "Noise Margin"
 value in the "Sort by:" slot.  Slide the mouse before
 releasing to sort by NETNAME. 
 *****************************************************
 
 This is simple an alphabetic ordering
 of the driver receiver pin-pairs per net. The Pin vs Net
 toggle controls whether "Next ..." increment to the next 
 driver receiver pin-pair within this same net, or to the 
 first pin pair on a completely new net. The other sort by
 choices allow users to focus in on a particular concern by
 sorting the results in order of the chosen value.

 Changing to the latest fastest technology, typically
 requires revisions in your the layout style.  Generally
 designers will want to shorten distances by using smaller
 components and finer line spacing.  This will help timing. 
 Also for the same net to net separations shorter nets collect 
 less crosstalk than longer nets. As you browse through the
 nets in this tutorial you will see that the longest nets
 tend to have the most problems.


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 Press <F1> to continue to next frame ...
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