 5.0 ANALYSIS TUTORIAL - SIGNAL INTEGRITY CONCEPTS
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The following 10 figures are an extremely brief introduction to the
concepts of digital signal integrity.  Each of these initial 10
figures was manually drawn to explain fundamental concepts.  These first
10 concept figures are NOT automated drawings or displays produced by Allegro.

Digital layouts propagate signals from Driver (output) to Receiver
(input) pins.  Digital data passed on data oriented nets are a sequence of 
0's and 1's where a specified low voltage range 
is recognized as a zero and a high voltage range is
recognized as a 1.  Other nets  such as clock lines are concerned
only with the edges (transitions from low-hi or hi-low voltages).
Conceptually the digital design assumes the signals being propagated
over the nets are stable lows, highs, or smooth transitions between these
stable (flat) voltage levels.

FIGURE 1 is a comparison of voltage over time waveforms such as
might be viewed on an oscilloscope probing your hardware prototype.
The red(left) trace shows a transition from a low to high logic level in
a smooth "idealized" form.  The green(right) trace shows a more typical real
world behavior where the transition is less than ideal. In many cases
the behavior at the driver pin itself is close to ideal but the
effects of the intervening vias, etch trace ... cause the observed
signal at the receiver pin to be degraded, 
showing real-world distortions similar to
the green waveform.  Signal
integrity analysis involves rules to limit the magnitude and timing of such 
distortions so the digital circuit will behave just as if the signals were
actually ideal.

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 The allowable signal distortion is specified data books for the component
technology (ASTTL, 100K_ECL, ...) being used
in the circuit design.  Specification rules generally apply to
the entire logic family, rules for all MOTOROLA-10K-ECL, all TI-LSTTL etc.

Figure 2 diagrams this concept of NOISE IMMUNITY.
Noise immunity is specified as the leeway between the narrow
range of logical low or high voltages guaranteed to be generated 
at the driver pins compared to the more generous range of voltages
still recognized unambiguously by the receiver pins.  Since a too high-high or too
low-low is not an ambiguity problem it is only the leeway towards the midrange which
defines the Noise Immunity.  Specifically the difference in the
data book specifications:

   The NOISE IMMUNITY leeway for a logical 1 = HIGH is:

                     VOHmin - VIHmin    

   (Volts Output Hi Minimum) - (Volts Input Hi Minimum)

   The NOISE IMMUNITY leeway for a logical 0 = LOW is:

                     VILmax - VOLmax    

   (Volts Input Low Maximum) - (Volts Output Low  Maximum)

The expected voltage noise must be smaller than this noise
immunity specification for the design to function reliably.

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The expected sources of noise can be predicted and budgeted for
in order to predict the final NOISE MARGIN.  
This Figure 3 diagrams how the NOISE MARGIN is the remaining leeway
taking the technology's intrinsic NOISE IMMUNITY minus all the 
noise expected for this particular layout.   
The green and gray bands represent budgeted or predicted magnitudes
of noise ingredients.  The small final NOISE MARGIN is the narrow
remaining leeway labeled in the figure below.
Large individual sources of noise (Conceptualized as the Green or Gray horizontally
filled bands) are undesirable.
For worst case consideration you must generally also assume that the
different sources of noise could add together.
A high intrinsic NOISE IMMUNITY and a high (or at least positive)
remaining NOISE MARGIN are the desirable design goals.  

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Figure 4. Defines the OVERSHOOT and UNDERSHOOT noise values. Undershoot
is towards the midrange, overshoot is an excursion to a too-high-high or
a too-low-low.  Undershoot contributes to ambiguity at the
receiver, recognizing the desired logic level.  Overshoot is a separate concern
for some technologies (such as ALS usage of Schottky diodes) where excessive
overshoot can fatally destroy components.  Other technologies can be
immune to overshoot.

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Figure 5. is a diagram of 2 nets on a layout, and how their parallelism
produces crosstalk.  Crosstalk is the noise occurring on a net, which is
produced by the switching activity of its neighbors. 
We expect some small crosstalk effects to "overflow" onto neighbor nets
due to the capacitive and inductive coupling of closely parallel
net segments.  This can be further observed to produce two 
separate crosstalk ingredients.  Signals propagate from Drivers
to Receivers on active neighbor nets.  As shown in this Figure 5,
forward crosstalk is
generated in the parallel segment in the same direction as the direction
of the active neighbor net, backward
crosstalk is generated in the reverse direction. Generally the backward crosstalk
is larger and of more concern than the forward crosstalk.

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Figure 6. provides some perspective on how the magnitude of the
crosstalk depends on the layout cross section and the separation between
the parallelism. This manually plotted diagram plots the Allegro predictions
(small rectangles) for parallelism between various cross-section 
configurations as a function (X axis) of increasing the parallel separation.
Only the dominant backwards crosstalk ingredient is shown.
Each of the 4 prediction
curves is color coded to 4 crosstalk configurations shown in
the cross-section diagram.  Micro or microstrip corresponds to the outermost
TOP or BOTTOM etch layers.  Strip or stripline etch is by definition surrounded
above and below by shield planes (shields such as a power or ground planes.) Buried microstrip is a layer which is not an outermost layer and only has a shield layer on
one side of it in the layer stackup.
Crosstalk does not occur between etch separated
by solid shield planes.  Crosstalk increases sharply as the separation
between the parallel etch decreases.  It is particularly high for
layer to layer proximities (flatter sides of Z axis cross-section
get close as opposed to just the thinner edges getting close for same layer
parallelism. The magnitude of the crosstalk is shown as a percentage
since crosstalk is proportional to the voltage swing (rise=low-to-high 
or fall= high-to-low)
on the active neighbor net.  

These prediction were manually plotted for
the case of very
long parallelism which produces a maximum backward crosstalk voltage, i.e.
whenever the parallel length is greater than or equal to a length delay
corresponding to half the time of the rise or fall.

Still longer, parallel lengths do NOT further increase the backwards
crosstalk voltage, they only
increase the duration of the backwards crosstalk noise.  
For net-to-net 
parallelism lengths shorter 
than this "saturation length" the backwards crosstalk is proportionally
smaller. I.e. for shorter parallelisms  1/3 the saturation length yields
1/3 the crosstalk, 1/8 the parallel length, 1/8th the crosstalk ...
For a fast 1 nanosecond rise or fall time the parallelism saturation length ranges from 
4 to 10 inches depending on the dielectric of the surrounding board materials.

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Figure 7. diagrams the calculation of the potential noise caused
by uneven temperatures between the driver pin component and the
receiver pin component.  Many technologies specify 
driver voltages and acceptable received voltages as a function
of temperature.  
Actually it is the junction(silicon die) temperature that matters not the temperature of
the component case.
Generally if both the driver and receiver components
are at the same temperature they will shift their 
voltage behavior identically and no thermal shift noise is produced.   
Thus what matters is the difference between the diagramed DriverShift and ReceiverShift
as a function of driver and receiver component temperatures.
Thermal shift noise tends to occur  
when board components connected to the same net
are at widely varying temperatures. It can also occur
even when board component temperatures are uniform if mixed component technologies
are in use.  Expected overall environment warming or cooling can cause
uneven shifts of voltage behavior between different technologies.

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The previous figures have focussed on noise in the voltage domain. The
layout of a design can also require concern in the time domain, i.e. to
make sure that the signals from the Drivers arrive at the receivers fast
enough to meet the overall timing requirements of the design.  
Figure 8 diagrams 3 different measures of delay from the time a Driver
pin initiates a switch of logic levels shown in red (a low-to-high "rise"is 
shown) until the time that this switch reaches the receiver pin shown in 
green.  

Three different measures of time are shown as being important:

PROPAGATION DELAY is the simplest. It is the time from the beginning
of the Driver voltage change until the beginning of the receiver voltage change.
This is a length only oriented delay, related to the "speed of light"
through the board dielectric materials per length per layer.  

FIRST SWITCH DELAY - Users really need to be
concerned even more concerned with the time until the receiver completes 
its switching.  This is diagrammed as the FIRST SWITCH DELAY. Note that
this is the separation between the time that an ideal driver, and the time
that the receiver crosses the receiver's threshold voltage.
The time for the driver rise is normally modeled as part of the functional gate
delay, not a portion of this First Switch interconnect delay.  

FINAL SETTLE DELAY
is the most pessimistic time.  FINAL SETTLE DELAY includes the time 
until the receiver voltage has "settled"
reliably outside of the midrange.  If the undershoot is small enough the
FINAL SETTLED DELAY is the same as the FIRST SWITCH DELAY.

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In typical digital designs the "edges" i.e. the low-to-high or high-to-low
transitions on clock nets control most of the circuit operation.
For clock lines it is not only important that the switching reach a
certain voltage threshold at the proper time, it is also crucial that each switch
be a smooth "monotonic" transition. If the transition is NON-MONOTONIC
as shown in Figure 9, this can cause "double clocking" where receiver
components can get out of synchrony with the proper circuit timing.
(The simplest example might have a Counter increment 1 too many. Any
bus structured design will fail to operate without reliable clocking.)
Any reversal in the switching change is undesirable in the midrange.  The
roller coaster "ringing" is not a problem if it is totally above VIHmin or
below VILmax.

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A rule of thumb for high speed designs is to require that the distortion
in the switching Rise or fall be small enough so that the complete transition
occurs at the receiver delayed only by the unavoidable ("speed of light")
propagation delay. Pin-to-pin interconnection lengths are controled to meet
specified rules.  However in addition to delays from interconnection length,
if the driver strength is too weak or the layout
fails to optimally carry the signal the transition might occur at the receiver
in steps.  Typically if the signal does not reach the receiver threshold
voltage after roughly the length oriented propagation delay, it will only continue to change
in steps, producing a switch at 3x (shown in Figure 10), 5x ... multiples of the
net's propagation
delay.  For complicated nets with branching and stubs ... the late switching
will could occur in still more complicated steps.

The goal of Allegro's First Incident switching check is to ignore minor
degradations in the received rise or fall time, but to catch the cases of
the transition received in much slower multiple steps.
Allegro simply flags
any cases when the time from the start of the driver change to reach the
switching voltage on the receiver is longer than 

       1.5 *  (IdealDriverRisetime + PropagationDelay)

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