 5.0 Analysis Tutorial - Finding marginal nets

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SNA reports and flags predicted noise which violates the user
controled "budget" of rules for tolerable voltage noise.  There are 
also separate rules to control pin to pin timing and smooth rise/falls.

Voltage noise may accumulate from several sources especially crosstalk 
and can cause design malfunction.  Each technology (TTL, ECL, GAS)
has intrinsic Noise Immunity which it can tolerate.  SNA predicts
each type of noise and subtracts their total from this Noise Immunity
to predict a remaining "Noise Margin".  "Noise margin" is your final 
margin of error.  You'd like it to remain large or at least positive.

Signal integrity data for 24 selected nets is now being presented, as
sorted to find the net with the lowest noise margin. There are no
major signal noise problems for these example nets.  Even the worst
signal (BUSCTRLL10 currently shown) has more than 30mV of remaining 
noise margin(see the DELAY & DISTORTION reported values). 
Even though the Backwards crosstalk has been *'ed as
a violation of its subrule, the result that the sum of all noise still leaves
a reasonable Noise margin means that for this net this substantial crosstalk
is marginally ok.  This budget for total noise thus provides the intelligence
to (if the user desires) allow a little extra crosstalk on nets that
can tolerate it because their other noise ingredients have been verified
to be small. 
Of course layout editing is still possible to strictly enforce a crosstalk alone
rule.  Each noise ingredient reduction will further increase the "Margin" of safety.

In the timing information section the rules have been set to 
flag several violations. The Switch delay rule requiring less than 1ns
is excessively small and nearly all pin-pairs show a "*" indicating
that this requested rule has been violated. Generally it is not
reasonable to request a switch delay (includes rise-or-fall time
distortion) which is less than the rule for propagation delay (length
per layer only).  Similarly the Maximum number of via rule set at 2 
fails for most pin-pairs for these nets.

Below you will need to be able to bring covered up windows to
the front for readability:

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 Hold down the middle mouse button with the cursor in the
 band at the top of this window and slide to the FRONT command
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 remember this is how to make any window come to the front, you'll need
this skill, any second now:

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 PICK THE "Param" MENU option, with the middle mouse button 
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 to view the current Rules setting. In the Delay and Distortion
 results you can see how the predictions are simply checked 
 against these rules ( *'ed if in violation such as "5*" vias). 

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 Left mouse pick  "Done" in the "Signal Analysis" parameter
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 form. (If you accidentally "Done" the execution form hit execute to
resurrect it.)

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 You should pick the "Next" and "Prev" 
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 buttons within the Signal
Analysis Execution form several times to see how you can step through the data.

 Note How:
   The driver: & receiver: pins change
   The Delay & Distortion results change:
   The hilited clines change (World view, & zoomed window.
   
 Also note how the predicted noise margin gets larger as you step "NEXT" through
the pin-pairs.  Perform a 
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 left button click in the upper right "World view" window 
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 This will pan your layout view to the area highlighting the net being analyzed.
The dashed white highlighting is the driver-to-receiver subset of
the net, the dashed red highlighting is the worst parallel segment on 
the worst neighbor net contributing to a "*"'ed violation of the 
Backward Crosstalk. Note that this segment contributing the peak
crosstalk does not have to be parallel along the driver-to-receiver 
portion of the net.  Crosstalk from anywhere on the net  CAN 
arrive as noise at the receiver pin.  Other rules such as propagation 
delay ARE limited to the driver to receiver subset path.  
You can cause the entire net to be hilited in a separate hilite
color than the pin-pin net subset.
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 Pick the (*)Net  toggle within the Signal Analysis Execution window
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 This will cause any portion of the current net outside
of the white hilited driver-receiver path to 
be highlighted yellow. Resetting to (*)pin will return to
only hilite the driver-to-receiver subset of the current net.

 If you (with the cursor in the "Layout:" window) 
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 hold down the right mouse button and slide the mouse 
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 you can pan the layout display to better see the current highlighted net and 
its neighbors. You can also jump the current window to a different region
with a right button pick within the "World View" window.

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 Press keyboard <F1> to continue to next help frame.
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