# syntax for a help file: # 1) a line beginning in a hash is ignored as a comment. # 2) a command name must be preceded by a '$' and be alone on that line. # 3) no other lines can begin with a '$'. # 4) the literal message to be printed follows the line with $cmdName. # # Define all of the set commands at the bottom of this file. $ destination_type DESTINATION Celltype of output netlist. DESTINATION [celltype] DESTINATION command is used for setting output celltype. Destination command will invoke the renamer. It is used when you want to create a cross reference table but you don't want to write out a netlist. Current foreign netlist types are [hil], [edf], [mdf], [vhd], [tdl], [elt]. Type Write ? for details. $ exit EXIT terminates utility EXIT Terminates this session in the netlist utility. Same as QUIT. $ flatten FLATTEN flattens the hierarchy of the last netlist READ. FLATTEN (options) Flattens the hierarchy of the netlist read in by the last READ command. The flattened version is not automatically written to a file, the WRITE command must be used. After flattening, both the original hierarchical and the flat version exist in memory. Flattening of netlist is automatically performed when a write command is issued without options. When writing foreign netlists, DO NOT execute flatten command alone. Use it with write (flat) [edf]cellname instead. There are two options for the flatten command: NORCS Suppresses RC data when flattening an [nle] for interconnect. INPUTDELAYS Recomputes RC input delays for qsim when flattening an [nle]. $ manager MANAGER opens a session with VLSImanager. MANAGER Opens a session with VLSImanager. This utility session will remain in its current state. When you type quit, you return to the orginal VLSInetlist session. $ signal_synonym SIGNAL_SYNONYM show synonym of specified signal names SIGNAL_SYNONYM [ ....] Shows the synonyms of the specified signals. This command is allowed only if translation has occured. Translation is automatically performed if the netlist type written out is different from the type read in. It can be explicitly specified using DEST command. $ instance_synonym INSTANCE_SYNONYM show synonym of specified instance names INSTANCE_SYNONYM [instance name> ....] Shows the synonyms of the specified instances. This command is allowed only if translation has occured. Translation is automatically performed if the netlist type written out is different from the type read in. It can be explicitly specified using DEST command. $ status STATUS status on pertaining things. STATUS Gives status on everything that has been set by the SET command, as well as names of cells that have been read in or to be written. $ quit QUIT terminates utility QUIT Terminates this session in the netlist utility. Same as EXIT. $ switch SWITCH read a [swt] switch cell, before the READ cmd. SWITCH cellname Reads a switch cell (celltype [swt]). The switch cell must be read before the READ command is given. If given after the READ, then the switch cell will have no effect. Global switching is done when the READ command is executed. Instance switching is done during the FLATTEN command. $ read READ read a netlist from a file. READ (options) [celltype]cellname Read a netlist from a file. If the design is hierarchical, then all levels of hierarchy will be read in. When a second READ command is issued, the previously read design is flushed from memory. If switching is desired, then the SWITCH command must be given before the READ. Currently allowed celltypes are [nls], [nle], [nlx], [nlf], [hns], [hnc], [fns], [fne], [fnx], [la], [sc], and [cp]. Default celltype is [nls]. VLSI netlist reads these foreign netlists : [hil] Reads flat. [edf] Reads V 200 level 0. [tdl] Reads flat. Parenthetical option: LAYOUT If netlist contains compiler subcells, create a routing netlist. ONELEVEL Only read the named cell, don't read its hierarchical subcells. SIM If netlist contains compiler subcells, create a simulation netlist. $ screen SCREEN enter the netlist screener utility. SCREEN Enter the netlist screener utility. $ spice SPICE enter the netlist-to-spice utility. SPICE Enter the netlist-to-spice utility. Type ? at the spice utility to get more help. The NL-to-SPICE utility converts an NL cell to a SPICE format. The SPICE format chosen can be suitable for HSPICE as well as for VLSISPICE. The structure of VLSI netlists can be mapped directly into HSPICE. $ split SPLIT enter the netlist-splitter utility. SPLIT The NL splitter utility splits an NL cell into several NL cells. This utility is useful when you use VLSI's Design Assistant to generate a netlist for multi-chip designs. As a first step in the process, you use the Design Assistant to partition the design into blocks and to define each block. Type ? at the vlsiSplit> prompt for more help. $ trim TRIM enter the netlist-to-spice trimmer utility. TRIM The NL trimmer utility extracts a subcircuit from an NL circuit description. Type ? to timmer promt to get more help. $ write WRITE write out a new netlist file. WRITE (options) [celltype]cellname Writes a new netlist file with the given name. A netlist must have been previously entered with the READ command. Unless an option is used, the flattened version of the netlist will be written. Currently allowed celltypes are [nls], [nle], [nlx], [nlf], [hns], [hnc], [fns], [fne], and [fnx]. The default celltype is [nls]. The default cellname is "xxx_f" where "xxx" was the cellname used in the READ command. Current foreign netlist types are [hil] Hierchical and Flat netlists are supported. Hilo Flat netlister will generate HFR, FSH automatically. [edf] Hierchical and Flat netlists are supported. Edif V 200 level 0. [mdf] Flat Only. The file generated is .EDIF not mdf. [vhd] HierarchicalOnly. [tdl] Flat Only. [elt] ELLA text: Hierchical and flat netlists are supported. There are five parenthetical options: TOP Write only the top level netlist for a VLSI netlist. Don't write out netlist for each of the subcells. HIER Use this option to write a non-VLSI hierarchical netlist. TREE Write all levels of the hierarchy for a VLSI format netlist. Each netlist will be written to a file of the given celltype, but of the original cellname. STRIP Strip extra node names while writing the file. The resulting netlist will only have one name per node. Only for VLSI formats. PIPEFLAT Flatten-into-pipe option. Calls the flattener and writes the flat netlist directly to a file without building an in-memory image. This may significantly speed flattening on large designs. Can't be used for foreign formats or [nle] files with RC delays. $ XREF XREF create a cross reference table. XREF (options) Cross reference table creates a table which corelates the names in the source netlist to those in the destination netlist. Translation should have occured, due to a WRITE or DEST command. The output cellName is the name specified in the command. If no name is specified, the name of the design is used. There are three parenthetical options : HIER Write the cross reference for every single hierarchical block in the design. FLAT Write the cross reference table for the flat description of design. TOP Write the cross reference table for the top level ports of design. This is default. # Define all of the set commands at the bottom of this file. $ set SET set up options for netlist translation. SET OptionName optionValue | ? Option name can be truncated as long as the truncated name is unique. Specifies various option values that may be needed when translating a netlists to other formats. SET sets up all default options if none set, also gives status on all options. SET ? for help. - Currently following options are implemented. Type SET optionName ? for detail help on a specific option. - Capacitance Set the actual or predictive capacitance FaultSimCell Set name for FSH file in HILO translation ReadPortOrder Specify port-ordered file to be read WritePortOrder Specify port-ordered file to be written sharedLibCap Adds instances of capactiance from the library. DeltaInfo Write out RC tree delay information - FOLLOWING ARE OPTIONS USED WITH WORKSTATIONS WSP Makes WSP from netlist or PMD if specified Also sets FileNameTopCell true(see below). Target Generate workstation RAM models. Type SET TAR ? XrefCells Compiled cells for which renaming of top level names is desired. PMD This is an obsolete option now. - FOLLOWING ARE OPTIONS USED WHEN WRITING EDIF EdifTargetType Specify the edif type. PropFile Specify cell correlating foreign properties to VLSI attributes in EDIF translation EdifWarningFile Name file to which EDIF warning messages are written FileNameTopCell Top cell name is changed to the filename if this option is set true. - FOLLOWING ARE OPTIONS USED WHEN WRITING Mach1000 Special_checks Perform special checks (setup & hold, etc) on Mach1000. - FOLLOWING ARE OPTIONS USED WHEN WRITING VHDL DerateValue - Derating factor to be used by models. VhdlDoc - Include behavioral descriptions of models. AbortOnWarnings - Set criteria for aborting VHDL translation. VhdlLibraryDumper - Generate a VHDL description of a library. createTestBench TRUE|FALSE - Generate accompanying testbench for design. tolerance [value] - - Acceptable time difference for testbench. VHDLVersion Std1076|Vantage|Zycad - Platform VHDL is to be compiled on. $ set capacitance CAPACITANCE sets the actualCapCellName [pst] or predCapCellName[sim] SET CAPACITANCE [celltype]cellname The cell is either actual or predictive. o actual capacitance cell: celltype of [pst] The cellName is the name of a post-simulation cell containing the actual capacitance of each net after place and route, such as [pst]design. The cell type is PST. o predictive capacitance cell: celltype of [sim] The cellName is the name of a predictive capacitance sim cell. This cell contains factors for VLSIexchange to predict the amount of capacitance each net will have after being placed and routed. $ set target SET TARGET workstation compiled ram models & wsps SET TARGET workstation Used for generating models of various workstation platforms. Type the name of the target workstation for which to generate output. Valid workstation types are: o - Carriage return will cancel the previous TARGET cmd. o DAISY - Daisy workstation model o HILO - HILO simulator model o MENTOR - Mentor Graphics workstation model o MACH1000 - Mach 1000 simulator model $ set wsp SET WSP TRUE|FALSE def is FALSE. makes WSP from netlist or pmd. SET WSP value The value is either TRUE or FALSE. If TRUE. Set wsp will create a [wsp]outputCellname, and will also create wsp cells of all rams.THIS OPTION ALSO SETS FILENAMETOPCELL TO TRUE. Please refer to VLSI's workstation documentation for more details. $ set special_checks SET SPECIAL_CHECKS TRUE|FALSE perform special checks (setup & hold, etc) on MACH 1000. (default is false) SET SPECIAL_CHECKS value This command is used for MACH 1000 EDIF netlists only. The value is either TRUE or FALSE. The MACH 1000 EDIF netlist that is generated will contain the commands for set-up and hold checks when special_checks is set to TRUE. $ set faultsimcell set faultsimcell cellname fault simulation command cell input, [fsh]file. set faultsimcell cellname fault simulation command cell input, [fsh]file. This command is used for HILO netlists only. The cellName is the name of the fault simulation command cell containing a specific list of faults to be injected for a HILO fault simulation. The cell type is FSH. This command also writes out a file called [hfr]cellname. HFR file contains cross reference of orginal names and Hilo names. $ set ReadPortOrder set ReadPortOrder [] [ ...] set ReadPortOrder [] [ ...] This command is used for reading in HILO or TEGAS netlists only. To read an implicit port order netlist, enter a port order cell name. You can have multiple port order cells to define all the cells in the design. The first port order cell is searched first, then the second and so on. If a cell is defined in two or more port order cells, the first definition found is used. $ set WritePortOrder set WritePortOrder [ ...] set WritePortOrder [ ...] This command is used for reading in HILO or TEGAS netlists only. To write an implicit port order netlist, enter a port order cell name. You can have multiple port order cells to define all the cells in the design. The first port order cell is searched first, then the second and so on. If a cell is defined in two or more port order cells, the first definition found is used. $ set pmd set PMD [...] Sets PMD name. set PMD [...] This command is no longer needed. Type SET WSP ? TARGET ? for more help. It is does not need to be specified for WSP or genrating model. $ set EdifWarningFile set EdifWarningFile set EdifWarningFile Normally all the edif reader warning messages are written to the screen These error messages can be redirected to a file by specifying the filename using this option. $ set sharedLibCap set sharedLibraryCapacitance True | False set sharedLibraryCapacitance default is False. Adds instances of capacitance from the shared library. The library must be on the search path. This command must be used before the read command. $ set deltaInfo set deltaInfo TRUE|FALSE set deltaInfo TRUE|FALSE If this option is used when writing out a netlist, a .txt file is written out. This file is similar in format to a [pst] file except that it contains additional information about RC tree delays. This option should be used only when an [nle] containing RC delay information is read in. $ set propfile set propfile set propfile Used by EDIF Reader. The edif reader users this file to match foreign properties to VLSI properties. The default is [txt]prop. # following used for edif writer. $ set FileNameTopCell set FileNameTopCell TRUE|FALSE set FileNameTopCell TRUE|FALSE Currently, this option is to be used when writing out edif netlist. In edif the top level design name can be different from the file name. Setting this option to true will result in a top cell with same name as the file name. THIS OPTION IS AUTOMATICALLY SET TRUE WHEN WSP IS TRUE. An example is: VLSInetlist> read [nls]cram01_pcl_l VLSInetlist> set FileNameTopcell true VLSInetlist> wr [edf]cram01_pcl. The design name is now cram01_pcl and not cram01_pcl_l. $ set XrefCell set XrefCell set XrefCell This option is used to rename the top level port names of a compiled cell which has been placed as an instance in a workstation created netlist. A cross reference file created by the XREF utility using the TOP option should exist. Multiple cells (separated by blanks) can be specified using this option. For example: VLSInetlist>read [nls]cram01_pcl_l VLSInetlist>set wsp true VLSInetlist>wr [edf]cram01_pcl VLSInetlist>xrf cram01_pcl This creates [xrf]cram01_pcl. When an hns from a workstation with an instance of cram01_pcl is to be read in by VLSInetlist, XrefCell should be set. VLSInetlist>set XrefCell cram01_pcl VLSInetlist>read [hns]workstationnetlist. $ set edifTargetType set edifTargetType set edifTargetType If this option is specified for the edif writer, the writer will generate information specific to the indicated target system. Currently recognised types are: VLSI ........ include instances of electrical primitives MENTOR ...... attach dangling nets to unconnected pins DAISY ....... tag all properties with owner "Daisy; use property global on Vdd/Vss and property outtype "T" on tristates; connect dangling nets to "z-dummy" ports If this option is specified for the edif reader, the reader will interpret information specific to the system that wrote the file. Currently recognised types are: SYNOPSYS .... watch for representation of Vdd/Vss as ports on special cells rather than global nets # FOLLOWING ARE OPTIONS USED WHEN WRITING VHDL $ set derateValue set derateValue value set derateValue value DEFAULT: 1.0 This option is only used by the VHDL writer. value specifies a real positive number that multiplies all delays used in the models. It is derived from temperature, voltage and derating curves for the particular technology used in the design. $ set vhdlDoc set vhdlDoc TRUE|FALSE set vhdlDoc TRUE|FALSE DEFAULT: True This option is only used by the VHDL writer. If TRUE is specified, then the VHDL netlist will also contain the behavioral descriptions of any primitives used in the design. If FALSE is specified, then the VHDL netlist will access compiled library elements that run under the VANTAGE workstation. The default is true. $ set abortOnWarnings set abortOnWarnings TRUE|FALSE set abortOnWarnings TRUE|FALSE DEFAULT: TRUE This option is only used by the VHDL writer. If value is FALSE then the translation process will NOT abort when warnings are issued to the user. NOTE: An incomplete VHDL netlist description may be generated if this option is set to FALSE. If value is TRUE then the translation process will be aborted if a complete VHDL description of the design CANNOT be generated. $ set VHDLLibraryDumper set VHDLLibraryDumper TRUE|FALSE set VHDLLibraryDumper TRUE|FALSE DEFAULT: FALSE This option is only used by the VHDL writer. This option should be set to TRUE inorder to generate a complete VHDL description of a library. Issuing a write statement followed by [vhd]libraryName will cause the VHDL behavioral description of all cells in libraryName to be written to the cell libraryName.vhd. $ set createTestBench set createTestBench TRUE|FALSE - This indicates whether a VHDL testbench is to be written out for the design. Note: testbenches may only be written out when VHDLVersion is set to Vantage or Std1076. Zycad does not support VLSI's testbench format. $ set tolerance set tolerance [value] - Value represents an acceptable integer time difference (in ns) that is encorporated into the VHDL testbench. Timing differences between the expected response and actual response of the design that are greater than this value will cause the testbench to report an error during simulation. This option is only used when the createTestBench option is set to TRUE. $set VHDLVersion set VHDLVersion Std1076|Vantage|Zycad - This specifies whether the VHDL that is written is to be run under the Vantage or Zycad platforms, or a platform that supports the full implementation of VHDL Std. 1076.