#!/bin/csh -f
# ctlsvtop.scr
#   script to generate ctlsvtop.v

alias BEGIN 'cat <<END'

set sel = "p1"
set tst = "p2"
set zin = "p3"
set sb_bg_n = "p4"
set partial_xfer = "p5"
set eosi = "p6"
set tmint = "p7"
set op_shift = "p8"
set ldctl = "p9"
set sv_en = "p10"
set donep = "p11"
set hnp_sel = "p12"
set sb_clk = "p13"
set sb_pa2 = "p14"
set sbus_err = "p15"
set incadr = "p16"
set sc2 = "p17"
set sc1 = "p18"
set sc0 = "p19"
set sld = "p20"
set decin = "p21"
set suspend = "p22"
set psd_rc = "p23"
set sync_out = "p24"
set sclr_n = "p25"
set pb_clk = "p26"
set sb_d15 = "p27"
set sb_d14 = "p28"
set sb_d13 = "p29"
set sb_d12 = "p30"
set sb_d11 = "p31"
set sb_d10 = "p32"
set sb_d9 = "p33"
set sb_d8 = "p34"
set sb_d7 = "p35"
set sb_d6 = "p36"
set sb_d5 = "p37"
set sb_d4 = "p38"
set sb_d3 = "p39"
set sb_d2 = "p40"
set sb_d1 = "p41"
set sb_d0 = "p42"
set cw_flg8 = "p43"
set hw_rd = "p44"
set hstop = "p45"
set od_ri = "p46"
set sb_pa3 = "p47"
set eofin = "p48"
set incout = "p49"
set sv_ld = "p50"
set int_imm = "p51"
set clr_suspend = "p52"
set imm_sync_in = "p53"
set s0 = "p54"
set s1 = "p55"


BEGIN

\`timescale 1 ns / 10 ps

module ctlsvtop (
	$sb_d15, $sb_d14, $sb_d13, $sb_d12,
	$sb_d11, $sb_d10, $sb_d9, $sb_d8,
	$sb_d7, $sb_d6, $sb_d5, $sb_d4,
	$sb_d3, $sb_d2, $sb_d1, $sb_d0,
	$int_imm, $imm_sync_in, $donep, $cw_flg8, $hw_rd, $incout,
	$hstop, $hnp_sel, $od_ri, $psd_rc,
	$sb_pa3, $sb_pa2,
	$sc2, $sc1, $sc0,
	$zin, $tst, $decin, $pb_clk,
	$ldctl, $sld, $sel, $op_shift, $incadr,
	$tmint, $eosi, $sbus_err, $sv_en, $sv_ld,
	$sb_bg_n, $sclr_n, $sb_clk, $clr_suspend,
	$partial_xfer, $suspend, $sync_out, $eofin,
	$s1, $s0
	) ;

	inout
		$sb_d15, $sb_d14, $sb_d13, $sb_d12,
		$sb_d11, $sb_d10, $sb_d9, $sb_d8,
		$sb_d7, $sb_d6, $sb_d5, $sb_d4,
		$sb_d3, $sb_d2, $sb_d1, $sb_d0;

	inout
		$hnp_sel;

	output
		$int_imm,
		$donep,
		$cw_flg8,
		$hw_rd,
		$incout,
		$hstop,
		$od_ri,
		$psd_rc,
		$sync_out,
		$clr_suspend;

	input
		$sc2,
		$sc1,
		$sc0,
		$sb_pa3,
		$sb_pa2,
		$imm_sync_in,
		$zin,
		$tst,
		$decin,
		$ldctl,
		$sld,
		$sel,
		$op_shift,
		$pb_clk,
		$incadr,
		$tmint,
		$eosi,
		$sbus_err,
		$sv_en,
		$sv_ld,
		$sb_bg_n,
		$partial_xfer,
		$suspend,
		$eofin,
		$sclr_n,
		$sb_clk,
		$s1,
		$s0;

	// Internal signals
	wire [15:0]
		sbdin,
		sbdout,
		sbdout1,
		sbdout2;
	wire
		svsel;

	padbx16 U100 (sbdin,
		{
		$sb_d15, $sb_d14, $sb_d13, $sb_d12,
		$sb_d11, $sb_d10, $sb_d9, $sb_d8,
		$sb_d7, $sb_d6, $sb_d5, $sb_d4,
		$sb_d3, $sb_d2, $sb_d1, $sb_d0
		},
		sbdout, sd_dr_n) ;

	dfntnb U107 (u107_q, u107_qn, sbd_dr_n, $sb_clk) ;
	ni01d5 U108 (sd_dr_n, u107_q) ;

	bd4 U103 (rd_in, $hw_rd, hw_rd, rd_dr_n) ;

	bd4 U104 (, $int_imm, int_imm_out, int_imm_dr_n) ;

	bd4 U105 (hnp_sel_in, $hnp_sel, hnp_sel_out, hnp_sel_dr_n) ;

	// delay sclr_n to avoid hold time violations in verilog
	ni01d1 U109 (sclr1_n, $sclr_n);
	ni01d1 U110 (sclr2_n, sclr1_n);
	ni01d1 U111 (sclr3_n, sclr2_n);

	// delay ldctl to avoid hold time violations in verilog
	ni01d1 U112 (ldctl1, $ldctl);
	ni01d1 U113 (ldctl2, ldctl1);
	ni01d1 U114 (ldctl3, ldctl2);

	// delay tmint to avoid hold time violations in verilog
	ni01d1 U115 (tmint1, $tmint);
	ni01d1 U116 (tmint2, tmint1);
	ni01d1 U117 (tmint3, tmint2);

	ctlsvchip U1 (.\sbdout[15] (sbdout [15]), .\sbdout[14] (sbdout [14]),
		.\sbdout[13] (sbdout [13]), .\sbdout[12] (sbdout [12]),
		.\sbdout[11] (sbdout [11]), .\sbdout[10] (sbdout [10]),
		.\sbdout[9] (sbdout [9]), .\sbdout[8] (sbdout [8]),
		.\sbdout[7] (sbdout [7]), .\sbdout[6] (sbdout [6]),
		.\sbdout[5] (sbdout [5]), .\sbdout[4] (sbdout [4]),
		.\sbdout[3] (sbdout [3]), .\sbdout[2] (sbdout [2]),
		.\sbdout[1] (sbdout [1]), .\sbdout[0] (sbdout [0]),
		.zin($zin), .tst($tst), .sel($sel),
		.\sbdin[15] (sbdin [15]), .\sbdin[14] (sbdin [14]),
		.\sbdin[13] (sbdin [13]), .\sbdin[12] (sbdin [12]),
		.\sbdin[11] (sbdin [11]), .\sbdin[10] (sbdin [10]),
		.\sbdin[9] (sbdin [9]), .\sbdin[8] (sbdin [8]),
		.\sbdin[7] (sbdin [7]), .\sbdin[6] (sbdin [6]),
		.\sbdin[5] (sbdin [5]), .\sbdin[4] (sbdin [4]),
		.\sbdin[3] (sbdin [3]), .\sbdin[2] (sbdin [2]),
		.\sbdin[1] (sbdin [1]), .\sbdin[0] (sbdin [0]),
		.\sc[2] ($sc2), .\sc[1] ($sc1), .\sc[0] ($sc0),
		.sld($sld), .incadr($incadr), .ldctl(ldctl3),
		.op_shift($op_shift), .decin($decin), .pb_clk($pb_clk),
		.tmint(tmint3), .eosi($eosi), .sbus_err($sbus_err),
		.sv_en($sv_en), .sv_ld($sv_ld),
		.sclr_n(sclr3_n), .int_imm_out(int_imm_out),
		.hw_rd(hw_rd), .rd_in(rd_in), .incout($incout),
		.cw_flg8($cw_flg8),
		.donep($donep), .psd_rc($psd_rc), .od_ri($od_ri),
		.hstop($hstop), .sb_bg_n($sb_bg_n),
		.\sb_pa[3] ($sb_pa3), .\sb_pa[2] ($sb_pa2),
		.hnp_sel_in(hnp_sel_in), .hnp_sel_out(hnp_sel_out),
		.sbd_dr_n(sbd_dr_n),
		.sb_clk($sb_clk), .clr_suspend($clr_suspend),
		.partial_xfer($partial_xfer), .suspend($suspend),
		.sync_out($sync_out), .imm_sync_in($imm_sync_in),
		.hnp_sel_dr_n(hnp_sel_dr_n),
		.int_imm_dr_n(int_imm_dr_n),
		.rd_dr_n(rd_dr_n),
		.eofin($eofin) ) ;

endmodule

/* 16 bit bidirect pad with common enable */
module padbx16 (c, pad, i, oen) ;

        output [15:0]
                c;
        inout [15:0]
                i;
        input [15:0]
                pad;
        input
                oen;

        bd4 U0 (c [0], pad [0], i [0], oen) ;
        bd4 U1 (c [1], pad [1], i [1], oen) ;
        bd4 U2 (c [2], pad [2], i [2], oen) ;
        bd4 U3 (c [3], pad [3], i [3], oen) ;
        bd4 U4 (c [4], pad [4], i [4], oen) ;
        bd4 U5 (c [5], pad [5], i [5], oen) ;
        bd4 U6 (c [6], pad [6], i [6], oen) ;
        bd4 U7 (c [7], pad [7], i [7], oen) ;
        bd4 U8 (c [8], pad [8], i [8], oen) ;
        bd4 U9 (c [9], pad [9], i [9], oen) ;
        bd4 U10 (c [10], pad [10], i [10], oen) ;
        bd4 U11 (c [11], pad [11], i [11], oen) ;
        bd4 U12 (c [12], pad [12], i [12], oen) ;
        bd4 U13 (c [13], pad [13], i [13], oen) ;
        bd4 U14 (c [14], pad [14], i [14], oen) ;
        bd4 U15 (c [15], pad [15], i [15], oen) ;
 
endmodule
 

END
