#!/bin/csh -f
# datatop.src
#   script to generate datatop.v

alias BEGIN 'cat <<END'

set sv_on = "p1"
set sb_sz2 = "p2"
set sb_sz1 = "p3"
set sb_sz0 = "p4"
set pb_d7 = "p5"
set pb_d6 = "p6"
set pb_d5 = "p7"
set pb_d4 = "p8"
set pb_d3 = "p9"
set pb_d2 = "p10"
set pb_d1 = "p11"
set pb_d0 = "p12"
set sb_clk = "p13"
set sdr = "p14"
set sld = "p15"
set sc2 = "p16"
set sc1 = "p17"
set sc0 = "p18"
set dr = "p19"
set immed = "p20"
set ps8 = "p21"
set ps16 = "p22"
set pspty = "p23"
set sb_bg_n = "p24"
set sclr_n = "p25"
set pb_clk = "p26"
set sb_dh7 = "p27"
set sb_dh6 = "p28"
set sb_dh5 = "p29"
set sb_dh4 = "p30"
set sb_dh3 = "p31"
set sb_dh2 = "p32"
set sb_dh1 = "p33"
set sb_dh0 = "p34"
set sb_dl7 = "p35"
set sb_dl6 = "p36"
set sb_dl5 = "p37"
set sb_dl4 = "p38"
set sb_dl3 = "p39"
set sb_dl2 = "p40"
set sb_dl1 = "p41"
set sb_dl0 = "p42"
set op_data = "p43"
set flg8 = "p44"
set op_shift = "p45"
set pc1 = "p46"
set pc0 = "p47"
set eofin = "p48"
set sv_sel = "p49"
set eofout = "p50"
set sb_sel = "p51"
set sb_as = "p52"
set ptr_inc = "p53"
set s0 = "p54"
set s1 = "p55"



BEGIN

\`timescale 1 ns / 10 ps

module datatop (
	$pb_d7, $pb_d6, $pb_d5, $pb_d4,
	$pb_d3, $pb_d2, $pb_d1, $pb_d0,
	$sb_dh7, $sb_dh6, $sb_dh5, $sb_dh4,
	$sb_dh3, $sb_dh2, $sb_dh1, $sb_dh0,
	$sb_dl7, $sb_dl6, $sb_dl5, $sb_dl4,
	$sb_dl3, $sb_dl2, $sb_dl1, $sb_dl0,
        $sv_on, $sv_sel, $op_shift,
        $sb_sz2, $sb_sz1, $sb_sz0, 
	$sc2, $sc1, $sc0, $pc1, $pc0,
	$sb_sel, $sb_as, $flg8, $pspty,
        $ps16, $ps8, $dr, $pb_clk, $sclr_n, $sb_clk, $sld, $sdr,
        $immed, $eofout, $eofin, $op_data, $sb_bg_n, $ptr_inc,
	$s1, $s0
	) ;

        inout
		$pb_d7,
		$pb_d6,
		$pb_d5,
		$pb_d4,
		$pb_d3,
		$pb_d2,
		$pb_d1,
		$pb_d0,
		$sb_dh7,
		$sb_dh6,
		$sb_dh5,
		$sb_dh4,
		$sb_dh3,
		$sb_dh2,
		$sb_dh1,
		$sb_dh0,
		$sb_dl7,
		$sb_dl6,
		$sb_dl5,
		$sb_dl4,
		$sb_dl3,
		$sb_dl2,
		$sb_dl1,
		$sb_dl0,
                $sb_sz2,
                $sb_sz1,
                $sb_sz0;

        output
                $sv_on,
                $sv_sel;
        input   
                $sc2,
                $sc1,
                $sc0,
                $pc1,
                $pc0,
                $sb_sel,
                $sb_as,
                $flg8,
                $op_shift,
                $pspty,
                $ps16,
                $ps8,
                $dr,
                $pb_clk,
                $sclr_n,
                $sb_clk,
                $sld,
                $sdr,
                $immed,
                $eofout,
                $eofin,
                $op_data,
                $sb_bg_n,
                $ptr_inc,
		$s1,
		$s0;

        // Internal signals
        wire [7:0]
                pdout,
                pdin,
                sdho,
                sdlo,
                sdhi,
                sdli;
        wire [2:0]
                sb_szin;
	wire
                pden_n,
                sden_n;

        // Bidirectional signals
//      in01d3 U101 (pden_n, pden) ;
        padbx8 U100 (pdin,
		{
		$pb_d7, $pb_d6, $pb_d5, $pb_d4,
		$pb_d3, $pb_d2, $pb_d1, $pb_d0
		},
		pdout, pden_n) ;

//      in01d5 U104 (sden_n, sden) ;
        padbx8 U102 (sdhi,
		{
		$sb_dh7, $sb_dh6, $sb_dh5, $sb_dh4,
		$sb_dh3, $sb_dh2, $sb_dh1, $sb_dh0
		},
		sdho, sd_dr_n) ;

        padbx8 U103 (sdli, 
		{
		$sb_dl7, $sb_dl6, $sb_dl5, $sb_dl4,
		$sb_dl3, $sb_dl2, $sb_dl1, $sb_dl0
		},
		sdlo, sd_dr_n) ;

	dfntnb U107 (u107_q, u107_qn, $sdr, $sb_clk) ;
	ni01d5 U108 (sd_dr_n, u107_qn) ;

	// generate inverted sb_clk
	in01d5 U109 (sb_clk_n, $sb_clk) ;

        // SBus size
        bd4 U104 (sb_szin [2], $sb_sz2, 1'b1, size_dr_n) ;
        bd4 U105 (sb_szin [1], $sb_sz1, 1'b0, size_dr_n) ;
        bd4 U106 (sb_szin [0], $sb_sz0, 1'b0, size_dr_n) ;

        // delay sclr_n to avoid hold time violations in verilog
        ni01d1 U110 (sclr1_n, $sclr_n);
        ni01d1 U111 (sclr2_n, sclr1_n);
        ni01d1 U112 (sclr3_n, sclr2_n);

        // delay to avoid hold time violations in verilog
        ni01d1 U113 (pspty1, $pspty);
        ni01d1 U114 (pspty2, pspty1);
        ni01d1 U115 (pspty3, pspty2);

        // delay to avoid hold time violations in verilog
        ni01d1 U116 (ps161, $ps16);
        ni01d1 U117 (ps162, ps161);
        ni01d1 U118 (ps163, ps162);

        // delay to avoid hold time violations in verilog
        ni01d1 U119 (ps81, $ps8);
        ni01d1 U120 (ps82, ps81);
        ni01d1 U121 (ps83, ps82);

        // delay to avoid hold time violations in verilog
        ni01d1 U122 (dr1, $dr);
        ni01d1 U123 (dr2, dr1);
        ni01d1 U124 (dr3, dr2);

dataregs U1 (.pb_clk($pb_clk), .sb_clk_n(sb_clk_n), .\pc[1] ($pc1 ),
	.\pc[0] ($pc0 ), .eofin($eofin), .immed($immed),
	.eofout($eofout), .op_data($op_data), 
	.flg8($flg8), .sv_on($sv_on), .\sb_sz[2] (sb_szin[2] ),
	.\sb_sz[1] (sb_szin[1] ), .\sb_sz[0] (sb_szin[0] ),
	.sb_as($sb_as), .sb_sel($sb_sel), 
	.sv_sel($sv_sel), .pspty(pspty3), .ps16(ps163), .ps8(ps83), .dr(dr3),
	.sb_bg_n($sb_bg_n),
	.\pd_out[7] (pdout[7] ), .\pd_out[6] (pdout[6] ), 
	.\pd_out[5] (pdout[5] ), .\pd_out[4] (pdout[4] ),
	.\pd_out[3] (pdout[3] ), .\pd_out[2] (pdout[2] ),
	.\pd_out[1] (pdout[1] ), .\pd_out[0] (pdout[0] ),
	.pdata_dr_n(pden_n),
	.\sdh_out[7] (sdho[7] ), .\sdh_out[6] (sdho[6] ),
	.\sdh_out[5] (sdho[5] ), .\sdh_out[4] (sdho[4] ),
	.\sdh_out[3] (sdho[3] ), .\sdh_out[2] (sdho[2] ),
	.\sdh_out[1] (sdho[1] ), .\sdh_out[0] (sdho[0] ), 
	.\sdh_in[7] (sdhi[7] ), .\sdh_in[6] (sdhi[6] ),
	.\sdh_in[5] (sdhi[5] ), .\sdh_in[4] (sdhi[4] ),
	.\sdh_in[3] (sdhi[3] ), .\sdh_in[2] (sdhi[2] ),
	.\sdh_in[1] (sdhi[1] ), .\sdh_in[0] (sdhi[0] ),
	.\sdl_in[7] (sdli[7] ), .\sdl_in[6] (sdli[6] ), 
	.\sdl_in[5] (sdli[5] ), .\sdl_in[4] (sdli[4] ),
	.\sdl_in[3] (sdli[3] ), .\sdl_in[2] (sdli[2] ),
	.\sdl_in[1] (sdli[1] ), .\sdl_in[0] (sdli[0] ),
	.\sdl_out[7] (sdlo[7] ), .\sdl_out[6] (sdlo[6] ),
	.\sdl_out[5] (sdlo[5] ), .\sdl_out[4] (sdlo[4] ), 
	.\sdl_out[3] (sdlo[3] ), .\sdl_out[2] (sdlo[2] ),
	.\sdl_out[1] (sdlo[1] ), .\sdl_out[0] (sdlo[0] ),
	.\pd_in[7] (pdin[7] ), .\pd_in[6] (pdin[6] ),
	.\pd_in[5] (pdin[5] ), .\pd_in[4] (pdin[4] ),
	.\pd_in[3] (pdin[3] ), .\pd_in[2] (pdin[2] ), 
	.\pd_in[1] (pdin[1] ), .\pd_in[0] (pdin[0] ),
	.sclr_n(sclr3_n), .size_dr_n(size_dr_n),
	.\sc[2] ($sc2 ), .\sc[1] ($sc1 ), .\sc[0] ($sc0 ),
	.sld($sld), .op_shift($op_shift), .sdr($sdr),
	.ptr_inc($ptr_inc) );

endmodule


module padbx8 (c, pad, i, en_) ;

        output [7:0]
                c;
        inout [7:0]
                pad;
        input [7:0]
                i; 
        input
                en_;

        bd4 U1 (c [0], pad [0], i [0], en_) ;
        bd4 U2 (c [1], pad [1], i [1], en_) ;
        bd4 U3 (c [2], pad [2], i [2], en_) ;
        bd4 U4 (c [3], pad [3], i [3], en_) ;
        bd4 U5 (c [4], pad [4], i [4], en_) ;
        bd4 U6 (c [5], pad [5], i [5], en_) ;
        bd4 U7 (c [6], pad [6], i [6], en_) ;
        bd4 U8 (c [7], pad [7], i [7], en_) ;
 
endmodule
 

END

