#!/bin/csh -f
# fsmtop.src
#   script to generate fsmtop.v

alias BEGIN 'cat <<END'

set suspend = "p1"
set sb_ack2 = "p2"
set sb_ack1 = "p3"
set sb_ack0 = "p4"
set param_dr_n = "p5"
set eosi = "p6"
set sv_on = "p7"
set op_shift = "p8"
set ptr_inc = "p9"
set sv_sel = "p10"
set sdr = "p11"
set eofin = "p12"
set sb_clk = "p13"
set sb_pa = "p14"
set hstop = "p15"
set sb_bg_n = "p16"
set clr_suspend = "p17"
set pdav = "p18"
set psd = "p19"
set donep = "p20"
set immed = "p21"
set prom_dr_n = "p22"
set eofout = "p23"
set iosel = "p24"
set ifc_rst_n = "p25"
set pb_clk = "p26"
set sb_br_n = "p27"
set flg8 = "p28"
set cw = "p29"
set sld = "p30"
set sc2 = "p31"
set sc1 = "p32"
set sc0 = "p33"
set incadr = "p34"
set sbus_err = "p35"
set sv_en = "p36"
set ldctl = "p37"
set sb_lerr_n = "p38"
set pldec = "p39"
set pcwr = "p40"
set pspty = "p41"
set ps16 = "p42"
set ps8 = "p43"
set dr = "p44"
set pc1 = "p45"
set pc0 = "p46"
set tmint = "p47"
set sv_ld = "p48"
set rd = "p49"
set sclr_n = "p50"
set partial_xfer = "p51"
set sb_rd = "p52"
set sb_reset_n = "p53"
set s0 = "p54"
set s1 = "p55"


BEGIN

\`timescale 1 ns / 10 ps

module fsmtop (
	$sb_ack2, $sb_ack1, $sb_ack0, 
	$sc2, $sc1, $sc0,
	$pc1, $pc0,
	$param_dr_n, $incadr, $sld, $sb_rd, $sb_br_n, $sdr,
	$prom_dr_n, $sv_en, $sv_ld, $pldec,
	$eofout, $iosel, $ldctl,
	$op_shift, $pcwr, $tmint, $dr, $pspty, $ps16, $ps8, $sbus_err,
	$eosi, $sclr_n, $sb_bg_n, $rd, $hstop, $immed, $cw,
	$sb_clk, $sb_pa, $sv_sel, $donep, $sv_on, $pb_clk, $flg8, $pdav,
	$eofin, $psd, $sb_lerr_n, $clr_suspend, $suspend, $partial_xfer,
	$sb_reset_n, $ifc_rst_n, $ptr_inc,
	$s1, $s0
	) ;

	inout
		$sb_ack2,
		$sb_ack1,
		$sb_ack0,
		$sb_rd;

	output
		$pc1,
		$pc0,
		$sc2,
		$sc1,
		$sc0,
		$param_dr_n,
		$incadr,
		$sld,
		$sb_br_n,
		$sdr,
		$prom_dr_n,
		$sv_en,
		$sv_ld,
		$pldec,
		$eofout,
		$iosel,
		$ldctl,
		$op_shift,
		$pcwr,
		$tmint,
		$dr,
		$pspty,
		$ps16,
		$ps8,
		$suspend,
		$partial_xfer,
		$sclr_n,
		$sbus_err;
	input
		$eosi,
		$sb_bg_n,
		$rd,
		$hstop,
		$immed,
		$cw,
		$sb_clk,
		$sb_pa,
		$sv_sel,
		$donep,
		$sv_on,
		$pb_clk,
		$flg8,
		$pdav,
		$eofin,
		$psd,
		$clr_suspend,
		$sb_lerr_n,
		$sb_reset_n,
		$ifc_rst_n,
		$ptr_inc,
		$s1,
		$s0;

	// Internal signals
	wire [2:0]
		ack_out,
		ack_in;
	wire
		ack_dr_n,
		sb_rd_out,
		sb_rd_in;

	bd4 U100 (ack_in [0], $sb_ack0, ack_out [0], ack_dr_n) ;
	bd4 U101 (ack_in [1], $sb_ack1, ack_out [1], ack_dr_n) ;
	bd4 U102 (ack_in [2], $sb_ack2, ack_out [2], ack_dr_n) ;

	bd4 U104 (sb_rd_in, $sb_rd, sb_rd_out, $param_dr_n) ;

	// this buffer allows a virtual pullup on sb_lerr_n
	//   without screwing up the Sbus monitor
	bd4 U105 (lerr_in, $sb_lerr_n, 1'b0, 1'b1) ;

        // generate inverted sb_clk
        in01d5 U109 (sb_clk_n, $sb_clk) ;

        // generate inverted pb_clk
        in01d5 U110 (pb_clk_n, $pb_clk) ;

	fsmchip U1 (.sb_bg_n($sb_bg_n), .rd($rd), .eosi($eosi),
		.hstop($hstop), .immed($immed), .cw($cw),
		.\ack_in[2] (ack_in[2]), .\ack_in[1] (ack_in[1]),
		.\ack_in[0] (ack_in[0]), .sb_clk_n(sb_clk_n),
		.sb_rd_in(sb_rd_in), .sv_on($sv_on), .flg8($flg8),
		.pdav($pdav), .eofin($eofin), .psd($psd),
		.param_dr_n($param_dr_n), .sld($sld),
		.sb_rd_out(sb_rd_out),
		.sb_br($sb_br_n), .sdr($sdr), .sv_en($sv_en),
		.sv_ld($sv_ld),
		.ack_dr_n(ack_dr_n), .\ack_out[2] (ack_out[2]),
		.\ack_out[1] (ack_out[1]), .\ack_out[0] (ack_out[0]),
		.pldec($pldec), .\pc[1] ($pc1), .\pc[0] ($pc0),
		.eofout($eofout), .iosel($iosel), .op_shift($op_shift),
		.pcwr($pcwr), .tmint($tmint), .\sc[2] ($sc2),
		.\sc[1] ($sc1), .\sc[0] ($sc0), .pb_clk_n(pb_clk_n),
		.incadr($incadr), .sb_lerr(lerr_in),
		.sbus_err($sbus_err),
		.ldctl($ldctl),
		.donep($donep), .sb_pa($sb_pa), .prom_dr_n($prom_dr_n),
		.dr($dr), .ps8($ps8), .ps16($ps16), .pspty($pspty),
		.sv_sel($sv_sel), .clr_suspend($clr_suspend),
		.suspend($suspend), .partial_xfer($partial_xfer),
		.sb_reset_n($sb_reset_n), .sclr_n($sclr_n),
		.ifc_rst_n($ifc_rst_n), .ptr_inc($ptr_inc) );

endmodule


END
