task	test_sctlfsm;

		begin

		// turn on scan signal
		scan_on = 1;

		// -> 4
		sb_reset_n = 0; #cycle;
		sb_reset_n = 1;

		// 4 -> 8
		#cycle;

		// 8 -> 8
		hstop = 1; #cycle;

		// 8 -> 5
		hstop = 0; #cycle; hstop = 1;

		// 5 -> 5
		#cycle;

		// 5 -> 5
		sb_bg_n = 0; #cycle;

		// 5 -> 6
		sb_bg_n = 0; #cycle;

		// 6 -> 6 -> 0
		sb_bg_n = 1; #(2 * cycle);

		// 0 -> 0
		//   !immed & !rd, set bus req
		//   also set done
		donep = 1; #cycle; donep = 0;

		// 0 -> 0 -> 2
		sb_bg_n = 0; #(2 * cycle);

		// 2 -> 2 -> 0
		sb_bg_n = 1; #(2 * cycle);

		// 0 -> ... -> 8
		//   dones should be set
		#cycle;

		// 8 -> 5
		//   set halt
		hstop = 0; ifc_rst_n = 0; #cycle;
		hstop = 1; ifc_rst_n = 1;

		// 5 -> 5 -> 4
		//   do reset
		#(4 * cycle);

		// 4 -> 8
		#cycle;

		// 8 -> 5
		hstop = 0; #cycle; hstop = 1;

		// 5 -> 6
		sb_bg_n = 0; #(3 * cycle);

		// 6 -> 3
		sb_ack = 3'h4; #cycle; sb_ack = 3'hz;

		// 3 -> 3
		#cycle; sb_bg_n = 1; #cycle;

		// 3 -> 5
		#cycle;

		// 5 -> 6
		sb_bg_n = 0; #(3 * cycle);

		// 6 -> 3
		//   set suspend
		sb_ack = 3'h6; #cycle; sb_ack = 3'hz;

		// 3 -> 3; clear suspend
		#(2 * cycle); clr_suspend = 1; #cycle;
		clr_suspend = 0;

		// 3 -> 5
		sb_bg_n = 1; #(2 * cycle);

		// 5 -> 6
		sb_bg_n = 0; #(3 * cycle);

		// 6 -> 6 -> 0
		sb_bg_n = 1; #cycle;
		sb_ack = 3'h3; #cycle; sb_ack = 3'hz;

		// 0 -> 8
		//   set cam wait
		cw = 1; #cycle;

		// test cw bit
		// 8 -> 8
		cw = 0; #cycle;

		// 8 -> 8
		cw = 1; #cycle;

		// 8 -> 0
		//   turn off scan
		scan_on = 0; #(3 * cycle);

		// 0 -> 0
		immed = 1; rd = 1; #cycle;

		// 0 -> A
		immed = 0; sb_bg_n = 0; #(2 * cycle);

		// A -> 1
		sb_ack = 3'h4; #cycle; sb_ack = 3'hz;

		// 1 -> 1 -> 0
		sb_bg_n = 1; #(2 * cycle);

		// 0 -> 0 -> 4
		//   set halt
		hstop = 0; ifc_rst_n = 0; #cycle;
		hstop = 1; ifc_rst_n = 1; hstop = 0;
		#(4 * cycle);

		// 4 -> 8
		#cycle;

		// 8 -> 0
		waitst_mainprc;

		// 0 -> 8
		sb_lerr_n = 1; #cycle;

		// 8 -> 8
		clr_suspend = 1; #cycle; clr_suspend = 0;

		// 8 -> 0
		waitst_mainprc;

		// 0 -> 2
		rd = 0; sb_bg_n = 0; #(2 * cycle);

		// 2 -> 1 (error ack on 1st word)
		sb_ack = 3'h6; #cycle; sb_ack = 3'hz;

		// 1 -> 1 -> 0
		sb_bg_n = 1; #(2 * cycle);
		clr_suspend = 1; #cycle; clr_suspend = 0;

		// 0 -> 2
		rd = 0; sb_bg_n = 0; #(2 * cycle);

		// 2 -> 2 (set partial_xfer)
		sb_ack = 3'h3; #cycle;
		sb_ack = 3'h6; #cycle; sb_ack = 3'hz;

		// 2 -> 0
		sb_bg_n = 1; #(2 * cycle);

		// 0 -> 8
		// partial_xfer is set
		#cycle;

		// 8 -> 8
		clr_suspend = 1; #cycle; clr_suspend = 0;

		// 8 -> 0
		waitst_mainprc;

		end

	endtask