92c92 < tri [n - 1:0] #20 --- > tri [n - 1:0] 94,97d93 < tri [n - 1:0] #20 < sad = saa, < sbd = sba; < 98a95,96 > sad, > sbd, 92,95d91 < tri [n - 1:0] #20 < sad = saa, < sbd = sba; < 96a93,94 > sad, > sbd, 49d48 < n_dl_c, 93,96d91 < tri [n - 1:0] #20 < sad = saa, < sbd = sba; < 97a93,94 > sad, > sbd, 104,141d100 < wire < bus_wr_n, < rd_en_n, < wr_en_n, < rd_dr_n, < wr_dr_n; < < bd4 U500 ( , n_dl [7], n_dl_c [7], rd_dr_n); < bd4 U501 ( , n_dl [6], n_dl_c [6], rd_dr_n); < bd4 U502 ( , n_dl [5], n_dl_c [5], rd_dr_n); < bd4 U503 ( , n_dl [4], n_dl_c [4], rd_dr_n); < bd4 U504 ( , n_dl [3], n_dl_c [3], rd_dr_n); < bd4 U505 ( , n_dl [2], n_dl_c [2], rd_dr_n); < bd4 U506 ( , n_dl [1], n_dl_c [1], rd_dr_n); < bd4 U507 ( , n_dl [0], n_dl_c [0], rd_dr_n); < bd4 U508 ( , n_dl_c [7], n_dl [7], wr_dr_n); < bd4 U509 ( , n_dl_c [6], n_dl [6], wr_dr_n); < bd4 U510 ( , n_dl_c [5], n_dl [5], wr_dr_n); < bd4 U511 ( , n_dl_c [4], n_dl [4], wr_dr_n); < bd4 U512 ( , n_dl_c [3], n_dl [3], wr_dr_n); < bd4 U513 ( , n_dl_c [2], n_dl [2], wr_dr_n); < bd4 U514 ( , n_dl_c [1], n_dl [1], wr_dr_n); < bd4 U515 ( , n_dl_c [0], n_dl [0], wr_dr_n); < < // mpa [4] is data direction (0 = read) < // mpb [4] is data enable (0 = enable) < // generate read and write enables < pullup (mpa [4]); < pulldown (mpb [4]); < in01d1 U250 (bus_wr_n, mpa [4]); < or02d1 U251 (rd_en_n, mpa [4], mpb [4]); < ni01d3 U252 (rd_dr_n, rd_en_n); < or02d1 U253 (wr_en_n, bus_wr_n, mpb [4]); < ni01d3 U254 (wr_dr_n, wr_en_n); < < // status-input < pulldown (mpb [0]); < 143,144c102,103 < ni01d1 U200 (lsout, mpa [1]) ; < pulldown (mpa [1]) ; --- > ni01d1 U200 (lsout, mpb [0]) ; > pulldown (mpb [0]) ; 151,152c110,111 < assign ioout = mpb [6] ; < pulldown (mpb [6]) ; --- > assign ioout = mpa [1] ; > pulldown (mpa [1]) ; 154,157d112 < // tie scan output to scan input using bidirect < // buffer which is always enabled < bd4 U300 (, mpb [7], mpa [7], 1'b0); < 159a115,119 > > // this signal is pulled up on module 0, > // down on all others > // ni01d1 U201 (cam_status, mpa [0]) ; > // pullup (mpa [0]) ; 1115a1116 > /* 4 delays for LPL and FPL*/ 1133,1150d1133 < in01d1 < u529 (u529_zn, fpl); < in01d1 < u484 (u484_zn, lpl); < nd02d1 < u534 (fly_sel, u529_zn, lpl); < nd02d1 < u535 (lut_sel, fpl, u484_zn); < mx21d1 < u448 (gl_data2, u502_q, u540_q, data_sel); < mx21d1 < u475 (lut_out2, u524_q, u526_q, lut_sel); < mx21d1 < u457 (f_data2, u509_q, u541_q, fly_sel); < mx21d1 < u390 (un_data2, u492_q, u488_q, data_sel); < mx21d1 < u439 (h_data2, u501_q, u496_q, data_sel); 1151a1135,1148 > u545 (u545_q, , u545_q, lut_out, sa, clk, u482_zn); > mfctnb > u541 (u541_q, , u541_q, f_data, sa, clk, u482_zn); > mfctnb > u550 (u550_q, , u550_q, u545_q, sa, clk, u482_zn); > mfctnb > u549 (u549_q, , u549_q, u541_q, sa, clk, u482_zn); > mfctnb > u548 (u548_q, , u548_q, u540_q, sa, clk, u482_zn); > mfctnb > u547 (u547_q, , u547_q, u496_q, sa, clk, u483_zn); > mfctnb > u546 (u546_q, , u546_q, u488_q, sa, clk, u483_zn); > mfctnb 1158c1155 < u541 (u541_q, , u541_q, f_data, sa, clk, u482_zn); --- > u539 (u539_q, , u539_q, h_data_in, sa, clk, u483_zn); 1162c1159 < u486 (u486_q, , u486_q, u538_q, sa, clk , u483_zn); --- > u486 (u486_q, , u486_q, u538_q, sa, clk, u483_zn); 1166c1163 < u539 (u539_q, , u539_q, h_data_in, sa, clk, u483_zn); --- > u488 (u488_q, , u488_q, un_data1, sa, clk, u483_zn); 1170,1171d1166 < u488 (u488_q, , u488_q, un_data1, sa, clk, u483_zn); < mfctnb 1184c1179 < u526 (u526_q, , u526_q, lut_out, sa, clk, u482_zn); --- > u526 (u526_q, , u526_q, u550_q, sa, clk, u482_zn); 1188c1183 < u507 (u507_q, , u507_q, u541_q, sa, clk, u482_zn); --- > u507 (u507_q, , u507_q, u549_q, sa, clk, u482_zn); 1195a1191,1192 > u490 (u490_q, , u490_q, u546_q, sa, clk, u483_zn); > mfctnb 1198,1199d1194 < u490 (u490_q, , u490_q, u488_q, sa, clk, u483_zn); < mfctnb 1204c1199 < u498 (u498_q, , u498_q, u496_q, sa, clk, u483_zn); --- > u498 (u498_q, , u498_q, u547_q, sa, clk, u483_zn); 1206c1201,1219 < u504 (u504_q, , u504_q, u540_q, sa, clk, u482_zn); --- > u504 (u504_q, , u504_q, u548_q, sa, clk, u482_zn); > mx21d1 > u448 (gl_data2, u502_q, u540_q, data_sel); > mx21d1 > u475 (lut_out2, u524_q, u545_q, lut_sel); > mx21d1 > u457 (f_data2, u509_q, u541_q, fly_sel); > mx21d1 > u390 (un_data2, u492_q, u488_q, data_sel); > mx21d1 > u439 (h_data2, u501_q, u496_q, data_sel); > nd02d1 > u534 (fly_sel, u529_zn, lpl); > nd02d1 > u535 (lut_sel, fpl, u484_zn); > in01d1 > u529 (u529_zn, fpl); > in01d1 > u484 (u484_zn, lpl); 1981c1994 < u347 (u347_zn, vw_int, u328_z, u344_zn, u346_z); --- > u347 (u347_zn, vw_int, iosel_n, u344_zn, u346_z); 2216c2229,2230 < \testen_n[1] , \testen_n[0] , nbf, alt, rmr_ld, als, q20, d, sre); --- > \testen_n[1] , \testen_n[0] , nbf, alt, rmr_ld, als, > q20, d, sre, op_clr_n); 2222c2236 < alt, rmr_ld, d; --- > alt, rmr_ld, d, op_clr_n; 2272a2287,2288 > mfctnb > u300 (nbf, , nbf, \q[13] , op_clr_n, clk, u218_zn); 2276c2292 < \u202$2 (sre, u217_zn, u216_zn, clk, nbf, u218_zn); --- > \u202$2 (sre, u217_zn, u216_zn, clk, \q[13] , u218_zn); 2278c2294 < \u202$3 (nbf, u217_zn, u216_zn, clk, \q[12] , u218_zn); --- > \u202$3 (\q[13] , u217_zn, u216_zn, clk, \q[12] , u218_zn); 2319c2335 < \regslt_n[1] , ld_modsel, modsel_en, dlen_ld2_n, \regslt_n[25] , --- > \regslt_n[1] , ld_modsel, modsel_en, st_modsel2, \regslt_n[25] , 2325c2341 < dlen_ld2_n, sre; --- > st_modsel2, sre; 2456,2457d2471 < in01d1 < u255 (u255_zn, dlen_ld2_n); 2501c2515 < u260 (u260_zn, u242_qn, u184_zn, u243_q, u255_zn); --- > u260 (u260_zn, u242_qn, u184_zn, u243_q, st_modsel2); 2503c2517 < u242 (u242_q, u242_qn, u255_zn, clk, u200_zn); --- > u242 (u242_q, u242_qn, st_modsel2, clk, u200_zn); 2522c2536 < ld_msr, ld_kick, st_lut_io, st_evc, lsout); --- > ld_msr, ld_kick, st_lut_io, st_evc, lsout, st_modsel, seq_mode); 2525c2539 < clk, clr, iosel_n, d, lsin, selected, lsout; --- > clk, clr, iosel_n, d, lsin, selected, lsout, seq_mode; 2529c2543,2544 < op_clr_n, w_r, st_scan_io, ld_msr, ld_kick, st_lut_io, st_evc; --- > op_clr_n, w_r, st_scan_io, ld_msr, ld_kick, > st_lut_io, st_evc, st_modsel; 2531d2545 < 2651a2666,2667 > or02d1 > u407 (u407_z, selected, seq_mode); 2653c2669,2671 < u379 (dlen_ld_n, iosel_n, selected, u325_qn); --- > u379 (dlen_ld_n, iosel_n, u407_z, u325_qn); > an02d1 > u406 (st_modsel, iosel_n, u325_qn); 3036,3037c3054,3056 < data_valid, iosel_n, int7, ld_modsel, dlen_ld2_n, seq_mode, ld_msr, < reg_shift_ext, inc_lir); --- > data_valid, iosel_n, int7, ld_modsel, st_modsel2, seq_mode, ld_msr, > reg_shift_ext, inc_lir, lsin, \ecl[4] , \ecl[3] , \ecl[2] , > \ecl[1] , \ecl[0] , st_modsel, selected); 3042c3061,3062 < ld_msr, reg_shift_ext; --- > ld_msr, reg_shift_ext, lsin, \ecl[4] , \ecl[3] , \ecl[2] , \ecl[1] , > \ecl[0] , st_modsel, selected; 3045c3065 < reg_shift, data_valid, int7, ld_modsel, dlen_ld2_n, inc_lir; --- > reg_shift, data_valid, int7, ld_modsel, st_modsel2, inc_lir; 3048,3067d3067 < or02d1 < u120 (u120_z, sior_stat, u115_z); < or02d1 < u153 (reg_shift, u120_z, u151_z); < nd02d1 < u118 (u118_zn, w_r, u101_zn); < nd02d1 < u129 (int7, u127_zn, u128_zn); < nd02d1 < u128 (u128_zn, u122_zn, u120_z); < nd02d1 < u119 (data_valid, u117_zn, u118_zn); < nd02d1 < u148 (u148_zn, u158_zn, ld_msr); < nd02d1 < u134 (ld_modsel, u148_zn, u143_zn); < nd02d1 < u155 (u155_zn, u157_zn, u154_zn); < nd02d1 < u127 (u127_zn, u126_zn, u125_zn); 3071,3073c3071 < u143 (u143_zn, seq_mode, u152_zn, u130_q); < in01d1 < u162 (inc_lir, u143_zn); --- > u190 (u190_zn, u122_zn, u158_zn, u120_z); 3075c3073 < u157 (u157_zn, u158_zn, u159_zn, u101_zn); --- > u143 (u143_zn, u183_z, u152_zn, u130_q); 3077c3075,3079 < u154 (u154_zn, seq_mode, u130_qn, u131_q); --- > u157 (u157_zn, u158_zn, u159_zn, st_modsel); > nd03d1 > u185 (st_modsel2, u157_zn, u163_zn, u184_zn); > nd03d1 > u189 (u189_zn, u126_zn, u158_zn, u125_zn); 3078a3081,3082 > u164 (u164_zn, u159_zn); > in01d1 3086a3091,3098 > u177 (u177_zn, \opc[2] ); > in01d1 > u178 (u178_zn, \opc[0] ); > in01d1 > u176 (u176_zn, \opc[4] ); > in01d1 > u166 (u166_zn, u165_zflag_n); > in01d1 3091c3103 < u156 (dlen_ld2_n, u155_zn); --- > u179 (u179_zn, ld_msr); 3092a3105,3106 > u126 (u126_zn, regsel_n); > in01d1 3095c3109 < u126 (u126_zn, regsel_n); --- > u158 (u158_zn, u183_z); 3098,3099c3112,3139 < in01d1 < u158 (u158_zn, seq_mode); --- > nd02d1 > u118 (u118_zn, w_r, u101_zn); > nd02d1 > u129 (int7, u189_zn, u190_zn); > nd02d1 > u119 (u119_zn, u117_zn, u118_zn); > nd02d1 > u134 (ld_modsel, u179_zn, u143_zn); > nd02d1 > u184 (u184_zn, u183_z, st_modsel); > or02d1 > u120 (u120_z, sior_stat, u115_z); > or02d1 > u186 (u186_z, u165_zflag_n, u151_z); > mx21d1 > u187 (reg_shift, u120_z, u186_z, u183_z); > mx21d1 > \u174$1 (\slen[4] , \len[4] , \ecl[4] , u175_z); > mx21d1 > \u174$2 (\slen[3] , \len[3] , \ecl[3] , u175_z); > mx21d1 > \u174$3 (\slen[2] , \len[2] , \ecl[2] , u175_z); > mx21d1 > \u174$4 (\slen[1] , \len[1] , \ecl[1] , u175_z); > mx21d1 > \u174$5 (\slen[0] , \len[0] , \ecl[0] , u175_z); > mx21d1 > u188 (data_valid, u119_zn, u191_z, u183_z); 3108a3149,3156 > ni01d1 > \u173$1 (\slen[6] , \len[6] ); > ni01d1 > \u173$2 (\slen[5] , \len[5] ); > ni01d1 > u183 (u183_z, seq_mode); > an05d1 > u175 (u175_z, u176_zn, \opc[3] , u177_zn, \opc[1] , u178_zn); 3122a3171,3174 > cntr7_dn > u165 (u167_zn, u142_zn, st_modsel2, clk, , , , , , , , > u165_zflag_n, \slen[6] , \slen[5] , \slen[4] , \slen[3] , > \slen[2] , \slen[1] , \slen[0] ); 3124a3177,3184 > nr02d1 > u167 (u167_zn, lsin, u166_zn); > an02d1 > u191 (u191_z, selected, u116_zn); > an02d1 > u181 (inc_lir, ld_modsel, u183_z); > nd04d1 > u163 (u163_zn, u183_z, u130_qn, u131_q, u164_zn); 3126a3187 > 3280c3341,3342 < st_evc, st_lut_io, evc_stat, lir_stat, sior_stat, op_clr_n); --- > st_evc, st_lut_io, evc_stat, lir_stat, sior_stat, op_clr_n, > \eclr[4] , \eclr[3] , \eclr[2] , \eclr[1] , \eclr[0] ); 3297c3359,3360 < clr_dly_n, evc_stat, lir_stat, sior_stat; --- > clr_dly_n, evc_stat, lir_stat, sior_stat, > \eclr[4] , \eclr[3] , \eclr[2] , \eclr[1] , \eclr[0] ; 3375c3438 < als, \reg_out[20] , u45_z, u20_sre); --- > als, \reg_out[20] , u45_z, u20_sre, op_clr_n); 3389c3452 < \regslt_n[1] , ld_modsel, modsel_en, u17_dlen_ld2_n, --- > \regslt_n[1] , ld_modsel, modsel_en, u17_st_modsel2, 3400c3463 < st_lut_io, st_evc, lsout); --- > st_lut_io, st_evc, lsout, st_modsel, u15_seq_mode); 3425,3426c3488,3491 < \int[7] , ld_modsel, u17_dlen_ld2_n, u15_seq_mode, u16_ld_msr, < \u18.reg_shift_ext , inc_lir ); --- > \int[7] , ld_modsel, u17_st_modsel2, u15_seq_mode, u16_ld_msr, > \u18.reg_shift_ext , inc_lir , lsin , \eclr[4] , > \eclr[3] , \eclr[2] , \eclr[1] , \eclr[0] , > st_modsel, u15_selected); 4197a4263 > parameter xpipe_dly = 7; //Tap the 8th flip-flop if FPL or LPL is set 4200c4266 < integer i; --- > integer i,j; 4219a4286 > dram_valid, 4221c4288,4289 < dram_busy; --- > dram_busy, > xpl; 4240a4309 > 4241a4311 > wr_addr, 4243,4245c4313,4316 < reg [15:0] < j, < addr_pipe[0:4]; --- > > reg [7:0] > addr_pipe[0:7]; > 4271d4341 < 4274a4345 > assign xpl = fpl | lpl; //Xtra pipeline if FPL or LPL 4277c4348,4349 < |(!w_r & scan_io & !scan_pipe[pipe_dly] & \sm[1] ) --- > |(!w_r & scan_io & !scan_pipe[pipe_dly] & \sm[1] & !xpl) > |(!w_r & scan_io & !scan_pipe[xpipe_dly] & \sm[1] & xpl) 4279c4351,4354 < |(!w_r & scan_io & !scan_pipe[pipe_dly] & !\sm[1] & (s==0)); --- > |(!w_r & scan_io & !scan_pipe[pipe_dly] & !\sm[1] & > (s==0) & !xpl) > |(!w_r & scan_io & !scan_pipe[xpipe_dly] & !\sm[1] & (s==0) > & xpl); 4281c4356,4358 < assign dram_valid = (!w_r & scan_pipe[pipe_dly] & \sm[1] ) --- > assign dram_valid = > (!w_r & scan_pipe[pipe_dly] & !xpl & \sm[1] ) > | (!w_r & scan_pipe[xpipe_dly] & xpl & \sm[1] ) 4283c4360,4361 < | (!w_r & (s==0) & scan_pipe[pipe_dly] & !\sm[1] ); --- > | (!w_r & (s==0) & scan_pipe[pipe_dly] & !xpl & !\sm[1] ) > | (!w_r & (s==0) & scan_pipe[xpipe_dly] & xpl & !\sm[1] ); 4286,4287c4364,4367 < | (!w_r & scan_io & !scan_pipe[pipe_dly] ) < | (!w_r & !lsin & scan_pipe[pipe_dly] ) --- > | (!w_r & scan_io & !scan_pipe[pipe_dly] & !xpl) > | (!w_r & scan_io & !scan_pipe[xpipe_dly] & xpl) > | (!w_r & !lsin & scan_pipe[pipe_dly] & !xpl ) > | (!w_r & !lsin & scan_pipe[xpipe_dly] & xpl ) 4290c4370,4372 < assign lta_valid = (!w_r & !lsin & scan_pipe[pipe_dly] ) --- > assign lta_valid = > (!w_r & !lsin & scan_pipe[pipe_dly] & !xpl) > | (!w_r & !lsin & scan_pipe[xpipe_dly] & xpl) 4298,4300c4380,4386 < assign scan_write = (w_r & cnt_pipe[pipe_dly] ) < | (!w_r & scan_pipe[pipe_dly] & !lsin & \sm[1] ) < | (!w_r & scan_pipe[pipe_dly] & !lsin & (s==0) & !\sm[1] ); --- > assign scan_write = > (w_r & cnt_pipe[pipe_dly] & !xpl) > | (w_r & cnt_pipe[xpipe_dly] & xpl) > | (!w_r & scan_pipe[pipe_dly] & !lsin & \sm[1] & !xpl) > | (!w_r & scan_pipe[xpipe_dly] & !lsin & \sm[1] & xpl) > | (!w_r & scan_pipe[pipe_dly] & !lsin & (s==0) & !\sm[1] & !xpl) > | (!w_r & scan_pipe[xpipe_dly] & !lsin & (s==0) & !\sm[1] & xpl); 4303a4390 > assign wr_addr = xpl ? addr_pipe[xpipe_dly] : addr_pipe[pipe_dly]; 4307,4308c4394,4401 < | (!w_r & scan_pipe[pipe_dly]); < assign dram_busy = scan_io | scan_in_prog | scan_pipe[pipe_dly]; --- > | (!w_r & scan_pipe[pipe_dly] & !xpl) > | (!w_r & scan_pipe[xpipe_dly] & xpl); > > assign dram_busy = > scan_io > | scan_in_prog > | (scan_pipe[pipe_dly] & !xpl) > | (scan_pipe[xpipe_dly] & xpl); 4330a4424,4426 > addr_pipe[7] = 0; > addr_pipe[6] = 0; > addr_pipe[5] = 0; 4347c4443,4445 < | (!w_r & scan_io & !scan_pipe[pipe_dly] & !\sm[1] & (s==0)) ) s=1; --- > |(!w_r & scan_io & !scan_pipe[pipe_dly] & !\sm[1] & (s==0) & !xpl) > |(!w_r & scan_io & !scan_pipe[xpipe_dly] & !\sm[1] & (s==0) & xpl) ) > s=1; 4359c4457 < if ((sm==2 | sm==3) & scan_shift & scan_write) --- > if ((sm==2 | sm==3) & scan_shift & scan_write & !xpl) 4361a4460,4462 > if ((sm==2 | sm==3) & scan_shift & scan_write & xpl) > dram[addr_pipe[xpipe_dly]] = cell_data; > 4364,4368c4465,4472 < scan_pipe[4] = #d scan_pipe[3]; < scan_pipe[3] = #d scan_pipe[2]; < scan_pipe[2] = #d scan_pipe[1]; < scan_pipe[1] = #d scan_pipe[0]; < scan_pipe[0] = #d scan_io | scan_in_prog; --- > if (scan_shift) scan_pipe[7] = #d scan_pipe[6]; > if (scan_shift) scan_pipe[6] = #d scan_pipe[5]; > if (scan_shift) scan_pipe[5] = #d scan_pipe[4]; > if (scan_shift) scan_pipe[4] = #d scan_pipe[3]; > if (scan_shift) scan_pipe[3] = #d scan_pipe[2]; > if (scan_shift) scan_pipe[2] = #d scan_pipe[1]; > if (scan_shift) scan_pipe[1] = #d scan_pipe[0]; > if (scan_shift) scan_pipe[0] = #d scan_io | scan_in_prog; 4370,4374c4474,4481 < cnt_pipe[4] = #d cnt_pipe[3]; < cnt_pipe[3] = #d cnt_pipe[2]; < cnt_pipe[2] = #d cnt_pipe[1]; < cnt_pipe[1] = #d cnt_pipe[0]; < cnt_pipe[0] = #d scan_cnt_en; --- > if (scan_shift) cnt_pipe[7] = #d cnt_pipe[6]; > if (scan_shift) cnt_pipe[6] = #d cnt_pipe[5]; > if (scan_shift) cnt_pipe[5] = #d cnt_pipe[4]; > if (scan_shift) cnt_pipe[4] = #d cnt_pipe[3]; > if (scan_shift) cnt_pipe[3] = #d cnt_pipe[2]; > if (scan_shift) cnt_pipe[2] = #d cnt_pipe[1]; > if (scan_shift) cnt_pipe[1] = #d cnt_pipe[0]; > if (scan_shift) cnt_pipe[0] = #d scan_cnt_en; 4375a4483,4485 > if (scan_shift) addr_pipe[7] = #d addr_pipe[6]; > if (scan_shift) addr_pipe[6] = #d addr_pipe[5]; > if (scan_shift) addr_pipe[5] = #d addr_pipe[4]; 4381a4492,4494 > if (scan_shift) disp_pipe[7] = #d disp_pipe[6]; > if (scan_shift) disp_pipe[6] = #d disp_pipe[5]; > if (scan_shift) disp_pipe[5] = #d disp_pipe[4]; 6186,6187c6299,6300 < "%h",pa,, < "%h",u40.addr_pipe[3],, --- > "%h",u40.phys_addr,, > "%h",u40.wr_addr,, 6200c6313,6323 < --- > $display("Pipeline",, > u11.u80.fpl, > u11.u80.lpl,, > u11.u80.sab_in, > u11.u80.sab1,, > u11.u80.lut_out, > u11.u80.lut_out2,, > u13.u18.par_en_n, > u13.u18.opc_clr_n, > u13.u18.u309.qn); > /* 6205c6328 < u13.u15.dlen_ld2_n, --- > u13.u15.st_modsel2, 6233,6235c6356,6367 < u13.u18.reg_shift_ext, < u13.u17.evc_stat ); < /* --- > u13.u17.reg_shift_ext, > u13.u17.evc_stat,, > u13.u17.u165.cnt_en, > u13.u17.u165.ld_cnt,, > u13.u17.u165.\q[6] , > u13.u17.u165.\q[5] , > u13.u17.u165.\q[4] , > u13.u17.u165.\q[3] , > u13.u17.u165.\q[2] , > u13.u17.u165.\q[1] , > u13.u17.u165.\q[0] ); > 6432c6564,6566 < u40_sior_stat, u13_op_clr_n); --- > u40_sior_stat, u13_op_clr_n, > \u10.ecl[4] , \u10.ecl[3] , \u10.ecl[2] , > \u10.ecl[1] , \u10.ecl[0] ); 7c7,11 < parameter cycle = 1000 ; --- > parameter > cycle = 1000, > edgetime = 500, > clockrise = 100, > clockfall = 200 ; 13,25d16 < always @(posedge system.pb_clk) < begin < #(cycle-1) ; < < $fstrobe (cvfile, < system.pb_eofout, < system.pb_dl [0], < system.pb_iosel, < system.pb_rst_n); < < < end < 28c19 < cvfile = $fopen (`CV_NAME) ; --- > cvfile = $fopen ("cam-test-vec.tbl") ; 29a21,79 > > $fdisplay (cvfile, "PINORDER -"); > $fdisplay (cvfile, "p1, -"); > $fdisplay (cvfile, "p2, -"); > $fdisplay (cvfile, "p3, -"); > $fdisplay (cvfile, "p4, -"); > $fdisplay (cvfile, "p5, -"); > $fdisplay (cvfile, "p6, -"); > $fdisplay (cvfile, "p7, -"); > $fdisplay (cvfile, "p8, -"); > $fdisplay (cvfile, "p9, -"); > $fdisplay (cvfile, "p10, -"); > $fdisplay (cvfile, "p11, -"); > $fdisplay (cvfile, "p12, -"); > $fdisplay (cvfile, "p13, -"); > $fdisplay (cvfile, "p14, -"); > $fdisplay (cvfile, "p15, -"); > $fdisplay (cvfile, "p16, -"); > $fdisplay (cvfile, "p17, -"); > $fdisplay (cvfile, "p18, -"); > $fdisplay (cvfile, "p19, -"); > $fdisplay (cvfile, "p20, -"); > $fdisplay (cvfile, "p21, -"); > $fdisplay (cvfile, "p22, -"); > $fdisplay (cvfile, "p23, -"); > $fdisplay (cvfile, "p24, -"); > $fdisplay (cvfile, "p25, -"); > $fdisplay (cvfile, "p26, -"); > $fdisplay (cvfile, "p27, -"); > $fdisplay (cvfile, "p28, -"); > $fdisplay (cvfile, "p29, -"); > $fdisplay (cvfile, "p30, -"); > $fdisplay (cvfile, "p31, -"); > $fdisplay (cvfile, "p32, -"); > $fdisplay (cvfile, "p33, -"); > $fdisplay (cvfile, "p34, -"); > $fdisplay (cvfile, "p35, -"); > $fdisplay (cvfile, "p36, -"); > $fdisplay (cvfile, "p37, -"); > $fdisplay (cvfile, "p38, -"); > $fdisplay (cvfile, "p39, -"); > $fdisplay (cvfile, "p40, -"); > $fdisplay (cvfile, "p41, -"); > $fdisplay (cvfile, "p42, -"); > $fdisplay (cvfile, "p43, -"); > $fdisplay (cvfile, "p44, -"); > $fdisplay (cvfile, "p45, -"); > $fdisplay (cvfile, "p46, -"); > $fdisplay (cvfile, "p47, -"); > $fdisplay (cvfile, "p48, -"); > $fdisplay (cvfile, "p49, -"); > $fdisplay (cvfile, "p50, -"); > $fdisplay (cvfile, "p51, -"); > $fdisplay (cvfile, "p52, -"); > $fdisplay (cvfile, "p53, -"); > $fdisplay (cvfile, "p54, -"); > $fdisplay (cvfile, "p55;"); > > 4c4 < 2 chip, 1 module per box, 2 box model */ --- > 2 chip, 2 box, 1 module per box model */ 11,12c11,12 < boxes = 2, // no. of boxes in system < mpb = 1, // no. of modules per box --- > boxes = 1, // no. of boxes in system > mpb = 2, // no. of modules per box 364a365,372 > > > > > > > > 16,19c16,17 < ("U96.cp", system.U1.U1.U1.u1.u125.u2.u96.cp, < "U96.d", system.U1.U1.U1.u1.u125.u2.u96.d, < "tmint.cp", system.U1.U3.U1.u1.u11.u8.u2.cp, < "tmint.q", system.U1.U3.U1.u1.u11.u8.u2.q --- > ("pb_rst_n", pb_rst_n, > "pb_clk", system.pb_clk,