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%%      \chapter{Overview}
%%      \chapter{Memory organization}
%%      \chapter{Registers}
%%      \chapter{Bit-plane operation}
%%      \chapter{Table operation}
%%      \chapter{Color map operation}
%%      \chapter{The event counter}
%%      \chapter{Diagnostics}
%%      \chapter{The user connector}
%%      \chapter{Multiple CAMs}
%%      \chapter{Gluing planes together}
%%      \chapter{Address and interrupt conflicts}
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\begin{titlepage}
\vspace*{12ex}
\begin{flushright}{\LARGE \bf
    CAM-6: \\ A High-Performance \\ Cellular Automata Machine \\ }
\end{flushright}
\vspace{8ex}
\begin{flushright}{\Huge \bf Hardware Manual\\}
                   \medskip
\end{flushright} 
\vspace{10ex}
\vfill
\begin{center}
{\Large Systems Concepts---San Francisco, CA \\ }
\end{center}
\vspace{2ex}
\centerline{Copyright \copyright\ 1987, 1989 Systems Concepts}
\end{titlepage}

\cleardoublepage		% start table of contents on odd page

\tableofcontents

\cleardoublepage

\listoftables

\cleardoublepage

\pagenumbering{arabic}


\chapter{Overview}

\Cam-6 (briefly, \cam) is a high-performance cellular automata machine
designed to be hosted by an IBM Personal Computer or compatible
unit (briefly, a \pc).  It is capable of
updating the entire cellular-automaton array every sixtieth of a second,
while simultaneously displaying the state of the array.

\Cam\ displays the state of its cells on a direct-drive color
monitor.  When a Color/Graphics Display Adapter (briefly, {\sl color card\/})
is used for the \pc's output, this card and the \cam\ card
may share a common \usedex{monitor}\index{external
video}.  In this case, the outputs from the color card are
connected to the video inputs of \cam, and \cam\ itself is connected to the
monitor;  a soft switch within \cam\ switches between the two video sources.
On \usedex{reset}, the switch is set to select the color card's output.

The monitor itself can be a CGA monitor or one downward compatible with it;
thus, EGA monitors and most multisync monitors will work.

\medskip

\Cam\ comprises four bit-planes, two lookup tables, a color map, and an
event counter.\index{plane}\index{lookup table}

Each cell is displayed as a single pixel.  Using four
bit-planes to represent the array allows each cell to assume one of
sixteen possible states.  These states are transformed by the color
map into one of sixteen colors.\index{color map}

\medskip

\Cam\ operates in one of two modes, namely {\sl display} and {\sl I/O}.
During \usedex{display mode} the four video signals in the monitor
cable, red, green, blue, and intensity, are generated by sequentially
reading the cell information from the bit-planes.  Each cell's content
is used as an index into the color map, which produces the four video
bits to be presented to the monitor.  At the same time as a cell is
processed for display, its content is also presented to the updating
circuitry that implements a cellular-automaton rule.  This allows \cam\
to update the entire array in one video frame time, 60 times per second.
During \usedex{io mode{I/O mode}} the bit-planes are accessible to the \pc\ for
read/write operations, while they are not accessible to the
display/update circuitry; however, \cam\ continues to generate
\usedex{sync} for the monitor.  The other data structures are accessible
to the \pc\ in both modes (though certain accesses are not meaningful or
desirable during display mode).

During display mode, \cam\ may execute steps\index{stepping}, where the
bit-planes are updated according to a given cellular-automaton rule.  A
step lasts an entire display frame, and is is performed by running the
contents of the bit-planes through the lookup tables to come up with the
new values of the cells in the bit-planes.  When not executing such an
updating or \usedex{active step}, \cam\ marks time; a display frame in
which no updating step occurs will occasionally be called an
\usedex{idle step}.  In what follows, a ``step'' will always mean an
{\sl active} one, unless ``idle'' is explicitly stated.

Interesting cell events can be counted during each step.\index{event counter}  The
color map is programmed to show the desired cells with the intensity
bit on; an occurence of this bit at any time during a step sets a flag in the
status register, and a 16-bit counter counts (modulo 256\by256=65,536) the number of occurences
during the step. The ambiguity between a count of 0 and one of
65,536 is resolved by the flag in the status register, which can also
be used to generate interrupts (cf.\ Section \ref{sec.color-map}).

A \usedex{user connector} is provided to connect external hardware to \cam\ to
expand its capabilities.  Up to eight \cam{}s may be used in a \pc, using
one \cam\ as a master and the other seven as slaves.\index{multiple cams}  A connector is
provided with signals to insure that all \cam{}s within a system are
properly synchronized.

\section{The bit planes}\index{plane}

Each bit-plane consists of an 8K-byte bit-mapped memory.  The memory is
arranged as 256 rows, each 32 bytes wide, resulting in a 256\by256
array.  During normal display the four bit-planes are used to select
colors from a 16-entry by 4-bit color map.  When \cam\ executes a step,
each cell and up to eight of its neighbors are used to look up the new
value of the cell in one of two programmable lookup tables.  The new
value is written back in the display memory, but it is displaced one row
down and one byte to the right.  The software must compensate for this
displacement when reading or writing the bit-planes after a step has
occurred.

A feature is provided for reading or writing an entire scan line of 32
bytes using the 8088 string move instructions.

\section{The lookup tables}\index{lookup table}

\Cam\ has two lookup tables, Table A and Table B, for computing the next
state of the bit-planes.  Table A provides the values for planes
0 and 1, while Table B provides values for planes 2 and 3.

A computation can be broken into several phases\index{phase}, to be
executed sequentially, one per frame-time.  This is done by storing
multiple functions in the tables and selecting the phase of
computation with the ``\usedex{phase bits}'' in the auxiliary
address register.

Some information about the horizontal and vertical position of a cell in
the array may also be used to address the lookup tables.  This
information consists of the two lowest bits of the row and column
addresses.  The lowest bit of either address can be programmed to appear
in true or negated form.  The resulting four bits are called {\sym H0},
{\sym V0}, {\sym H1}, and {\sym V1}. 

The \usedex{user connector} provides additional flexibility by allowing
external connection to the lookup table address lines.  If the lookup
tables are too small for an application, external logic can be
connected to bypass them and provide update data directly to the bit
planes.

Independent computations may be done in each bit plane, or the tables
may be programmed to permit inter-plane computations.

\section{The color map}\label{sec.color-map}\index{color map}

The color map translates the four bits coming from the bit-planes to
RGBI outputs.  An \usedex{event} detector is connected to the intensity
bit flag to permit the software or external hardware to recognize and react
to interesting events taking place during a step.  A 16-bit counter
records the number of events in a frame.\index{event counter}


\chapter{Memory Organization}\index{memory map}

\Cam\ is memory mapped to permit the use of memory-referencing
instructions, thereby increasing flexibility in the software.  \Cam\
normally occupies addresses {\hex DF800}--{\hex DFFFF} (all addresses
are in hexadecimal), as detailed in Table \ref{memmap}.  When additional
\cam{}s (up to 64) are added to a system, they occupy successively
\index{address conflict} lower 2K-byte blocks of memory.  For example,
the second \cam\ appears at addresses {\hex DF000}--{\hex DF7FF}.  See
Chapter \ref{multiCAM} for special installation information.

Eight registers are used to control \cam.  They occupy the first eight
bytes of \cam's address space, and are described in the
following chapter.

The remainder of \cam's address space is occupied by four data
structures: the four bit-planes, the two lookup tables, the color map,
and the event counter.

The bit-planes are addressed by row and column registers, {\sym PRA}
and {\sym PCA}.  References to the bit-planes are made through a data
register, {\sym PDAT}.  The low-order nine address bits of {\sym PDAT}
are don't-cares, so {\sym PDAT} appears in 512 consecutive bytes of
the address space.

The Plane Column Address register points to nybbles of the bit-planes
in a scan line;  it automatically increments by two after each
reference to the {\sym PDAT} register, allowing up to 32 bytes of data to be
transferred in one instruction using the 8088 {\tt MOVS} (move string)
instruction.

The \usedex{lookup table}s occupy 256 bytes of \cam\ address space.  Table A
appears in the right half of each byte, and Table B appears in the
left half.  The total size of the two tables is 4K bytes.  The high
four bits of the address come from a control register.

The \usedex{color map} occupies 16 bytes, and only the low nybble of each byte
contains data.

The \usedex{event counter} occupies one word.

\begin{table}
$$
\tabcolsep 2pt
\small\sym
\begin{tabular}{|c|l|c|c|c|c|c|c|c|c|c|}\hline
      &              &       & \multicolumn{8}{|c|}{\rm Bit} \\\cline{4-11}
\rm Name&\rm Addr.&\rm r/w& {\rm 7} & {\rm 6} & {\rm 5} & {\rm 4} & {\rm 3} & {\rm 2} & {\rm 1} & {\rm 0}\\\hline\hline	
SSR   & \hex DF800   & \rm R & EVENT & DPYLIN & VRUN & HRUN & STEPRQ & INTFLG & PROC & DIAG \\\hline
SRQ   & \hex DF801   & \rm W & STEPRQ & \multicolumn{7}{|c|}{\rm not used} \\\hline
CCR   & \hex DF802   & \rm W & USETAB & DPYRQ & VGLUE & HGLUE & LDTBL & INTENB & DPYNRM & CAMOUT \\ \hline
AAR   & \hex DF803   & \rm W & PCLB & PCLA & VC0 & HC0 & P3 & P2 & P1 & P0 \\\hline
TAA   & \hex DF804   & \rm W & TAC1 & TAM & TAS5 & TAS4 & TAS3 & TAS2 & TAS1 & TAS0 \\\hline
TBA   & \hex DF805   & \rm W & TBC1 & TBM & TBS5 & TBS4 & TBS3 & TBS2 & TBS1 & TBS0 \\\hline
PCA   & \hex DF806   & \rm W & \multicolumn{2}{|c|}{\rm not used} & \multicolumn{4}{c}{\rm Plane Column Address}
                                                                  & \multicolumn{2}{c|}{} \\\hline
PRA   & \hex DF807   & \rm W & \multicolumn{8}{|c|}{\rm Plane Row Address} \\\hline
CDAT  & \hex DFA00\rm-- & \rm W & \multicolumn{4}{|c|}{\rm not used} &\rm $-$Blue &\rm $-$Green &\rm $-$Red &\rm $-$Inten \\
      & \hex DFA0F   &       & \multicolumn{4}{|c|}{} & & & & \\\hline
CNTLO & \hex DFA00   & \rm R & \multicolumn{8}{|c|}{\rm Event Count (LSB)} \\\hline
CNTHI & \hex DFA01   & \rm R & \multicolumn{8}{|c|}{\rm Event Count (MSB)} \\\hline
TDAT  & \hex DFC00\rm-- & \rm both & TBD3 & TBD2 & TBD1 & TBD0 & TAD3 & TAD2 & TAD1 & TAD0 \\
      & \hex DFCFF   & & & & & & & & & \\\hline
PDAT  & \hex DFE00\rm-- & \rm both & \multicolumn{8}{|c|}{\rm Plane Data} \\
      & \hex DFFFF   &       & \multicolumn{8}{|c|}{} \\\hline
\end{tabular}
$$
\caption{\Cam\ memory map.}\label{memmap}
\end{table}


\chapter{Registers}\index{registers}

There are eight registers in \cam\ for control of display,
stepping, and reading and writing of the four bit-planes.
They are the main {\sl control and configuration} register ({\sym CCR}), the
{\sl step status} register ({\sym SSR}), the {\sl auxiliary address} register
({\sym AAR}), the {\sl step request} register ({\sym SRQ}), the {\sl Table A
address source-select} register ({\sym TAA}), the {\sl Table B address
source-select} register ({\sym TBA}), the {\sl plane row-address} register
({\sym PRA}), and the {\sl plane column-address} register ({\sym PCA}).  The
\symdex{SSR} is read-only; the rest of the registers are
write-only.

\section{Control and configuration register ({\sym CCR})}

The \symdex{CCR} is located at address {\hex DF802}.  When \cam\
is \usedex{reset} (by turning on the \pc), the {\sym CCR} control
bits are set to zero.  See Table \ref{CCR Bits} for a description of
the {\sym CCR} bits.


\section{Step status register ({\sym SSR})}

The \symdex{SSR} is located at address {\hex DF800}.
Status\index{status} bits in the {\sym SSR} are described in Table \ref{SSR
Bits}.

\section{Auxiliary address register ({\sym AAR})}

The \symdex{AAR} is located at address {\hex DF803}.  The
\symdex{AAR} bits are described in Table \ref{AAR Bits}.

\clearpage

\begin{table}[h]
$$
 \begin{tabular}{|c|c|p{4.30in}|}\hline
Bit & Name & \multicolumn{1}{c|}{Description} \\\hline\hline
 7 & \symdex{USETAB} & Use Table A outputs \symdex{TAD1} and
\symdex{TAD3} and Table B outputs \symdex{TBD1} and \symdex{TBD3}
instead of planes to drive the color map.  \\\hline
 6 & \symdex{DPYRQ} & Enter display mode.  This bit must be set for a
step to start.  Clearing this bit during a step will stop
the step and clobber data in the bit-planes.  Clearing this bit
during the \symdex{VRUN} period, when bit-plane data is being sent to
the monitor, will leave the plane address registers (\symdex{PCA} and
\symdex{PRA}) in a random state which should be corrected before {\sym
DPYRQ} is set again.  \\\hline
 5 & \symdex{VGLUE} & When appropriate connections are made to the
vertical \usedex{glue} connector, this bit enables the connection of
multiple planes to provide ``taller'' arrays.  See Chapter
\ref{ChapterGlue} for details.  \\\hline
 4 & \symdex{HGLUE} & When appropriate connections are made to the
horizontal \usedex{glue} connector, this bit enables the connection of
multiple planes to provide ``wider'' arrays.  See Chapter
\ref{ChapterGlue} for details.  \\\hline
 3 & \symdex{LDTBL} & Select the \pc\ as the source of the two low-order
address bits of the lookup tables.  When this bit is clear, the bit
planes' ``center'' bits are used to provide these bits.  \\\hline
 2 & \symdex{INTENB} & Setting this bit enables an interrupt on {\sym
IRQ2} at the beginning of vertical retrace.  Clearing this bit resets
the interrupt flag (bit 2 in the {\sym SSR}) and disables further
interrupts from the \cam\ system.  \\\hline
 1 & \symdex{DPYNRM} & With this bit clear, the vertical retrace
interval is lengthened by eight scan lines.  This changes the frame rate
from 60 Hz to 58 Hz.  \\\hline
 0 & \symdex{CAMOUT} & Selects the \cam\ system as the source of
\usedex{monitor} video.  With this bit clear, the \usedex{external
video} source is connected to the \usedex{monitor}.  \\\hline
 \end{tabular}
$$
\caption{Control and configuration register.}\label{CCR Bits}
\end{table}

\clearpage

\begin{table}[h] % Step status register
$$
 \begin{tabular}{|c|c|p{4.375in}|}\hline
Bit & Name & \multicolumn{1}{c|}{Description} \\\hline\hline
 7 & \symdex{EVENT} & The intensity bit of the display was on since the
last step started.  (The {\sl number} of such on bits is accumulated in the
event counter.)  \\\hline
 6 & \symdex{DPYLIN} & A frame is being displayed. \\\hline
 5 & \symdex{VRUN} & The \usedex{monitor} is in the vertically active
part of the screen (i.e.,  not in vertical retrace).  \\\hline
 4 & \symdex{HRUN} & The \usedex{monitor} is in the active part of the
scan line.  \\\hline
 3 & \symdex{STEPRQ} & A step has been requested. \\\hline
 2 & \symdex{INTFLG} & An interrupt condition has been raised.  \\\hline
 1 & \symdex{PROC} & A step is in progress. \\\hline
 0 & \symdex{DIAG} & A \usedex{diagnostic} condition (selected by {\sym
P0}--{\sym P1} in the \symdex{AAR}) is active.  See Chapter
\ref{ChapterDiag} for details.  \\\hline
 \end{tabular}
$$
\caption{Step status register.}\label{SSR Bits}
\end{table}

\begin{table}[h] % Auxiliary address register
$$
 \begin{tabular}{|c|c|p{4.75in}|}\hline
Bit & Name & \multicolumn{1}{c|}{Description} \\\hline\hline
 7 & \symdex{PCLB} & {\footnotesize This bit works in conjunction with the
\symdex{TBC1} bit in the \symdex{TBA} register to select the source of
input for planes 2 and 3 (see Table \ref{TBC1/PCLB}).  \symdex{PCLB} is
affected by the \symdex{USERB} pin on the user connector; see Chapter
\ref{UserConnector} for details.\par}  \\\hline
 6 & \symdex{PCLA} & {\footnotesize This bit works in conjunction with the
\symdex{TAC1} bit in the \symdex{TAA} register to select the source of
input for planes 0 and 1 (see Table \ref{TAC1/PCLA}).  \symdex{PCLA} is
affected by the \symdex{USERA} pin on the user connector; see Chapter
\ref{UserConnector} for details.\par}  \\\hline
 5 & \symdex{VC0} & {\footnotesize Reverses the polarity of vertical spatial parity bit
{\sym V0} (see Chapter \ref{TableOperation} for details).\par}  \\\hline
 4 & \symdex{HC0} & {\footnotesize Reverses the polarity of horizontal spatial
parity bit {\sym H0}.\par} \\\hline
 3--0 & {\sym P3\index{phase bits}}--{\sym P0} & {\footnotesize These bits provide four
functions: When loading the tables, {\sym P0}--{\sym P3} provide the
high-order address bits.  When reading or writing a plane, these bits
select which plane(s) are referenced.  For
diagnostics\index{diagnostic}, {\sym P0} and {\sym P1} select the source
of the \symdex{DIAG} bit in the \symdex{SSR} (see Chapter
\ref{ChapterDiag}).  During a step, these bits can be used to
select different parts of the lookup tables, allowing the user to
implement a sequence of steps using a different rule at each step;  for this reason, these
bits are known as ``phase bits.''\par}  \\ \hline
 \end{tabular}
$$
\caption{Auxiliary address register.}\label{AAR Bits}
\end{table}

\clearpage

\section{Step request register ({\sym SRQ})}\index{stepping}

The \symdex{SRQ} is located at address {\hex DF801}.  The
\symdex{SRQ} is used to initiate or cancel a step.  Writing
to the \symdex{SRQ} with bit 7 on causes a step to start at the
beginning of the next display cycle.  Writing a zero to the \symdex{SRQ}
before the step has started will cancel the request.  Writing a zero to
the \symdex{SRQ} after the step has started will cause the step to
stop at a random point in the planes, resulting in clobbered data.  This
register is automatically cleared at the end of a step.

\section{Table address registers ({\sym TAA} and {\sym TBA})}\index{lookup table}

The \symdex{TAA} and \symdex{TBA} registers are located at addresses
{\hex DF804} and {\hex DF805}.  {\sym TAA} controls table A; {\sym
TBA} controls table B.  The two tables are functionally identical.  Bit
7 in the \symdex{TAA} (\symdex{TBA}) is \symdex{TAC1} (\symdex{TBC1}),
and is described with the \symdex{PCLA} (\symdex{PCLB}) bit in Tables
\ref{TAC1/PCLA} and \ref{TBC1/PCLB}.  Bit 6 is \symdex{TAM}
(\symdex{TBM}), which selects the Margolus\index{Margolus neighborhood}
neighborhood for the lookup table addresses.  The remaining bits, {\sym
TAS0}--{\sym TAS5} ({\sym TBS0}--{\sym TBS5}), are used, when the Margolus
neighborhood is not active, to select different sources for the table addresses.  The use of
these bits is illustrated in Table \ref{TAS} through Table \ref{TBSM}.

\clearpage

\begin{table}[h]
$$
 \begin{tabular}{|c|c|c|c|}\hline
\multicolumn{2}{|c|}{use} & \multicolumn{2}{c|}{to set source for:} \\\hline
\symdex{TAC1} & \symdex{PCLA} & Plane 0 & Plane 1 \\\hline\hline
0 & 0 & \symdex{TAD0} & \symdex{TAD2} \\\hline
0 & 1 & \symdex{TAD1} & \symdex{TAD3} \\\hline
1 & 0 & \symdex{PDAT} & \symdex{PDAT} \\\hline
1 & 1 & \symdex{UI2} & \symdex{UI3} \\\hline
 \end{tabular}
$$
\caption{Table A output selection.}\label{TAC1/PCLA}
\end{table}


\begin{table}[h]
$$
 \begin{tabular}{|c||c|c|}\hline
{\sym LDTBL} & {\sym TAA01} & {\sym TAA00} \\ \hline \hline
0 & {\sym C1} & {\sym C0} \\ \hline
1 & {\sym A1} & {\sym A0} \\ \hline
 \end{tabular}
$$
$$
 \begin{tabular}{|c|c||c|c|c|c|}\hline
 {\sym TAS1} & {\sym TAS0} & {\sym TAA05} & {\sym TAA04} & {\sym TAA03} & {\sym TAA02} \\ \hline \hline
0 & 0 & {\sym A5} & {\sym A4} & {\sym A3} & {\sym A2} \\ \hline
0 & 1 & {\sym N1} & {\sym S1} & {\sym W1} & {\sym E1} \\ \hline
1 & 0 & {\sym NW0} & {\sym NE0} & {\sym SW0} & {\sym SE0} \\ \hline
1 & 1 & {\sym UA05} & {\sym UA04} & {\sym UA03} & {\sym UA02} \\ \hline
 \end{tabular}
$$
$$
 \begin{tabular}{|c|c||c|c|c|c|}\hline
 {\sym TAS3} & {\sym TAS2} & {\sym TAA09} & {\sym TAA08} & {\sym TAA07} & {\sym TAA06} \\ \hline \hline
0 & 0 & {\sym P1} & {\sym P0} & {\sym A7} & {\sym A6} \\ \hline
0 & 1 & {\sym N0} & {\sym S0} & {\sym W0} & {\sym E0} \\ \hline
1 & 0 & {\sym V0} & {\sym H0} & {\sym V1} & {\sym H1} \\ \hline
1 & 1 & {\sym UA09} & {\sym UA08} & {\sym UA07} & {\sym UA06} \\ \hline
 \end{tabular}
$$
$$
 \begin{tabular}{|c|c||c|c|}\hline
 {\sym TAS5} & {\sym TAS4} & {\sym TAA11} & {\sym TAA10} \\ \hline \hline
0 & 0 & {\sym P3} & {\sym P2} \\ \hline
0 & 1 & {\sym C3} & {\sym C2} \\ \hline
1 & 0 & {\sym V0} & {\sym H0} \\ \hline
1 & 1 & {\sym UA11} & {\sym UA10} \\ \hline
 \end{tabular}
$$
\caption{Table A address sources (``compass'' neighbors).}\label{TAS}
\end{table}

\clearpage

\begin{table}[h]
$$
 \begin{tabular}{|c||c|c|}\hline
{\sym LDTBL} & {\sym TAA01} & {\sym TAA00} \\ \hline \hline
0 & {\sym C1} & {\sym C0} \\ \hline
1 & {\sym A1} & {\sym A0} \\ \hline
 \end{tabular}
$$
$$
 \begin{tabular}{|c|c||c|c|c|c|c|c|}\hline
{\sym V0} & {\sym H0} & {\sym TAA07} & {\sym TAA06} & {\sym TAA05} & {\sym TAA04} & {\sym TAA03} & {\sym TAA02} \\ \hline \hline
0 & 0 & {\sym SE1} & {\sym S1} & {\sym E1} & {\sym SE0} & {\sym S0} & {\sym E0} \\ \hline
0 & 1 & {\sym SW1} & {\sym W1} & {\sym S1} & {\sym SW0} & {\sym W0} & {\sym S0} \\ \hline
1 & 0 & {\sym NE1} & {\sym E1} & {\sym N1} & {\sym NE0} & {\sym E0} & {\sym N0} \\ \hline
1 & 1 & {\sym NW1} & {\sym N1} & {\sym W1} & {\sym NW0} & {\sym N0} & {\sym W0} \\ \hline
 \end{tabular}
$$
$$
 \begin{tabular}{|c|c||c|c|}\hline
{\sym TAS3} & {\sym TAS2} & {\sym TAA09} & {\sym TAA08} \\ \hline \hline
0 & 0 & {\sym P1} & {\sym P0} \\ \hline
0 & 1 & {\sym N0} & {\sym S0} \\ \hline
1 & 0 & {\sym V0} & {\sym H0} \\ \hline
1 & 1 & {\sym UA09} & {\sym UA08} \\ \hline
 \end{tabular}
$$
$$
 \begin{tabular}{|c|c||c|c|}\hline
{\sym TAS5} & {\sym TAS4} & {\sym TAA11} & {\sym TAA10} \\ \hline \hline
0 & 0 & {\sym P3} & {\sym P2} \\ \hline
0 & 1 & {\sym C3} & {\sym C2} \\ \hline
1 & 0 & {\sym V0} & {\sym H0} \\ \hline
1 & 1 & {\sym UA11} & {\sym UA10} \\ \hline
 \end{tabular}
$$
\caption{Table A address sources (``Margolus'' neighbors).}\label{TASM}
\end{table}

\clearpage

\begin{table}[h] % B output selection
$$
 \begin{tabular}{|c|c|c|c|}\hline
\multicolumn{2}{|c|}{use} & \multicolumn{2}{c|}{to set source for:} \\\hline
\symdex{TBC1} & \symdex{PCLB} & Plane 2 & Plane 3 \\ \hline
0 & 0 & \symdex{TBD0} & \symdex{TBD2} \\\hline
0 & 1 & \symdex{TBD1} & \symdex{TBD3} \\\hline
1 & 0 & \symdex{PDAT} & \symdex{PDAT} \\\hline
1 & 1 & \symdex{UI2} & \symdex{UI3} \\\hline
 \end{tabular}
$$
\caption{Table B output selection.}\label{TBC1/PCLB}
\end{table}

\begin{table}[h] % B address sources (compass)
$$
 \begin{tabular}{|c||c|c|}\hline
{\sym LDTBL} & {\sym TBA01} & {\sym TBA00} \\ \hline \hline
0 & {\sym C3} & {\sym C2} \\ \hline
1 & {\sym A1} & {\sym A0} \\ \hline
 \end{tabular}
$$
$$
 \begin{tabular}{|c|c||c|c|c|c|}\hline
{\sym TBS1} & {\sym TBS0} & {\sym TBA05} & {\sym TBA04} & {\sym TBA03} & {\sym TBA02} \\ \hline \hline
0 & 0 & {\sym A5} & {\sym A4} & {\sym A3} & {\sym A2} \\ \hline
0 & 1 & {\sym N3} & {\sym S3} & {\sym W3} & {\sym E3} \\ \hline
1 & 0 & {\sym NW2} & {\sym NE2} & {\sym SW2} & {\sym SE2} \\ \hline
1 & 1 & {\sym UB05} & {\sym UB04} & {\sym UB03} & {\sym UB02} \\ \hline
 \end{tabular}
$$
$$
\begin{tabular}{|c|c||c|c|c|c|}\hline
{\sym TBS3} & {\sym TBS2} & {\sym TBA09} & {\sym TBA08} & {\sym TBA07} & {\sym TBA06} \\ \hline \hline
0 & 0 & {\sym P1} & {\sym P0} & {\sym A7} & {\sym A6} \\ \hline
0 & 1 & {\sym N2} & {\sym S2} & {\sym W2} & {\sym E2} \\ \hline
1 & 0 & {\sym V0} & {\sym H0} & {\sym V1} & {\sym H1} \\ \hline
1 & 1 & {\sym UB09} & {\sym UB08} & {\sym UB07} & {\sym UB06} \\ \hline
 \end{tabular}
$$
$$
 \begin{tabular}{|c|c||c|c|}\hline
{\sym TBS5} & {\sym TBS4} & {\sym TBA11} & {\sym TBA10} \\ \hline \hline
0 & 0 & {\sym P3} & {\sym P2} \\ \hline
0 & 1 & {\sym C1} & {\sym C0} \\ \hline
1 & 0 & {\sym V0} & {\sym H0} \\ \hline
1 & 1 & {\sym UB11} & {\sym UB10} \\ \hline
 \end{tabular}
$$
\caption{Table B address sources (``compass'' neighbors).}\label{TBS}
\end{table}

\clearpage

\begin{table}[h] % B address sources (Margolus)

$$
 \begin{tabular}{|c||c|c|}\hline
{\sym LDTBL} & {\sym TBA01} & {\sym TBA00} \\ \hline \hline
0 & {\sym C3} & {\sym C2} \\ \hline
1 & {\sym A1} & {\sym A0} \\ \hline
 \end{tabular}
$$
$$
 \begin{tabular}{|c|c||c|c|c|c|c|c|}\hline
{\sym V0} & {\sym H0} & {\sym TBA07} & {\sym TBA06} & {\sym TBA05} & {\sym TBA04} & {\sym TBA03} & {\sym TBA02} \\ \hline \hline
0 & 0 & {\sym SE3} & {\sym S3} & {\sym E3} & {\sym SE2} & {\sym S2} & {\sym E2} \\ \hline
0 & 1 & {\sym SW3} & {\sym W3} & {\sym S3} & {\sym SW2} & {\sym W2} & {\sym S2} \\ \hline
1 & 0 & {\sym NE3} & {\sym E3} & {\sym N3} & {\sym NE2} & {\sym E2} & {\sym N2} \\ \hline
1 & 1 & {\sym NW3} & {\sym N3} & {\sym W3} & {\sym NW2} & {\sym N2} & {\sym W2} \\ \hline
 \end{tabular}
$$
$$
 \begin{tabular}{|c|c||c|c|}\hline
{\sym TBS3} & {\sym TBS2} & {\sym TBA09} & {\sym TBA08} \\ \hline \hline
0 & 0 & {\sym P1} & {\sym P0} \\ \hline
0 & 1 & {\sym N2} & {\sym S2} \\ \hline
1 & 0 & {\sym V0} & {\sym H0} \\ \hline
1 & 1 & {\sym UB09} & {\sym UB08} \\ \hline
 \end{tabular}
$$
$$
 \begin{tabular}{|c|c||c|c|}\hline
{\sym TBS5} & {\sym TBS4} & {\sym TBA11} & {\sym TBA10} \\ \hline \hline
0 & 0 & {\sym P3} & {\sym P2} \\ \hline
0 & 1 & {\sym C1} & {\sym C0} \\ \hline
1 & 0 & {\sym V0} & {\sym H0} \\ \hline
1 & 1 & {\sym UB11} & {\sym UB10} \\ \hline
 \end{tabular}
$$
\caption{Table B address sources (``Margolus'' neighbors).}\label{TBSM}
\end{table}


\section{Plane address registers}\index{plane}

The Plane Address Registers are used to read and write the bit-planes,
and to set the picture origin for display.  The origin need not start
at coordinate $(0,0)$.  These registers are actually counters and are
used by the hardware to count through the bit-planes during display
and update.  These registers should not be written during the
\symdex{VRUN} interval as this will disrupt the display and,
if a step is in progress, clobber data.

\subsection{Plane column-address register ({\sym PCA})}

The \symdex{PCA} is located at address {\hex DF806}.  It addresses
the columns of the bit-planes for reading, writing, displaying, and
stepping.  The \symdex{PCA} addresses nybbles within a row.  Since there
are 32 bytes in a row, only the low six bits are significant.  This
register automatically increments during plane reading and writing, so
that consecutive bytes in the row of a bit-plane can be transferred with
the 8088 {\sym MOVS} (move string) instruction.  The counter counts
modulo 64, so that the auto-increment feature automatically wraps around
to the beginning of a row.  A \usedex{diagnostic} function is available
to check proper operation of this register.  After a step has
occurred, this register will have been incremented by 2, which
compensates for the picture's origin having moved one byte to the right.
The programmer may wish to keep track of this if he desires to read or
write the plane memory after one or more steps.

\subsection{Plane row-address register ({\sym PRA})}

The \symdex{PRA} is located at address {\hex DF807}.  The \symdex{PRA}
provides the high-order eight bits of address to the bit-planes.  Unlike
the \symdex{PCA}, the \symdex{PRA} does not auto-increment during plane
reading and writing and must be set up for every scan line of data read
or written.  After each step this register will have
been incremented by 1, which compensates for the picture's origin having
moved one scan line down.  The \symdex{PRA} also has \usedex{diagnostic}
read-back abilities.


\chapter{Bit-plane operation}\index{plane}

The bit-plane data register (\symdex{PDAT}) is located at
addresses {\hex DFE00} through {\hex DFFFF}.  That is, the low order
9 bits of address are intentionally don't-cares so that an 8088
string move operation can quickly read or write an entire row of bit-plane
data.

\section{Writing a bit-plane}\index{plane/io{I/O}}

To write a single byte, set the row and column of the desired byte in
the \symdex{PRA} and \symdex{PCA}.  Because the {\sym PCA} addresses
nybbles in the bit-planes' rows, the address written to this register
must be twice the byte address desired.  The plane to be written is
selected by the \usedex{phase bits} in the \symdex{AAR}.  Setting {\sym
P0} causes plane 0 to be written, {\sym P1} selects plane 1, etc.\ (see
Table \ref{PlaneWrite}).  If more than one bit is set, then each plane
selected will receive the same data.  Once this is done, the data can be
written to \symdex{PDAT} and the column counter is auto-incremented to
the next byte address.

\begin{table}[h]
$$
 \begin{tabular}{|c|c|}\hline
Phase bit set & Plane written \\ \hline \hline
{\sym P0} & 0 \\ \hline
{\sym P1} & 1 \\ \hline
{\sym P2} & 2 \\ \hline
{\sym P3} & 3 \\ \hline
 \end{tabular}
$$
\caption{Plane selection (writing)}\label{PlaneWrite}
\end{table}

Because of this auto-incrementing feature, up to 32 bytes of data (one
scan line) can be written to the bit planes without reloading the
counters.  Since stepping causes data in the planes to move one byte
to the right, the origin of a scan line may not be in column zero.
The \symdex{PCA} auto-incrementer reflects this: if data is
loaded starting in the middle of the scan line, the counters will wrap
around to the beginning of the same scan line.

\section{Reading a bit-plane}\index{plane/io}

To read from the bit-planes, the nybble address of the desired byte is
entered in the \symdex{PRA} and \symdex{PCA}.  The plane to read is
selected by {\sym P1} and {\sym P0} in the \symdex{AAR} (see Table
\ref{PlaneRead}).  The plane read/write hardware is a pipelined serial
data path.  An initial dummy read of \symdex{PDAT} is necessary to cause
bits to load from the bit-planes into the pipeline and ultimately into
the {\sym PDAT} register.  After this initial read, \symdex{PDAT} will
then contain the desired byte and \symdex{PCA} will increment to the
next column byte address.  The first byte read is undefined;  once this
byte is read, successive bytes will be valid.  Up to 32
consecutive bytes can be read in this way;  in other words, to read $n$
consecutive bytes, $n+1$ read operations must be executed, the first of
which returns an undefined value.  Whenever the \symdex{PCA} or
\symdex{PRA} is written with a new address, a dummy read must be done to
start the read hardware; valid data is read in the second byte.

\begin{table}[h]
$$
 \begin{tabular}{|c|c|c|}\hline
{\sym P1} & {\sym P0} & Plane Read \\ \hline \hline
0 & 0 & 0 \\ \hline
0 & 1 & 1 \\ \hline
1 & 0 & 2 \\ \hline
1 & 1 & 3 \\ \hline
 \end{tabular}
$$
\caption{Plane selection (reading)}\label{PlaneRead}
\end{table}

\section{Setting up for display mode}\index{display mode}

After a \usedex{reset}, the video switch will be set to display the
\usedex{external video} source (typically a color card).  The
\symdex{CAMOUT} bit in the \symdex{CCR} must be set to select \cam\ as
the source of video.  It may take several hundred milliseconds for the
\usedex{monitor} to lock to the \usedex{sync} generated by \cam.  It may
be necessary to adjust the monitor's\index{monitor} horizontal and
vertical hold controls to stabilize and center the picture.

When the \symdex{DPYNRM} bit in the \symdex{CCR} is set, \cam\ provides
a vertical-retrace interval equal to eight scan lines; some
monitors\index{monitor} may not be able to retrace in this amount of
time, in which case a few display lines at the top of the frame may be lost. 
Clearing \symdex{DPYNRM} increases the retrace
interval to 16 scan line times (and decreasing the refresh frequency to
approximately 58 Hz).  Because the retrace interval is doubled, the
software has much more time to change \cam\ parameters between steps.
When operating in this mode, it may not be possible to use the same
vertical-hold setting for both the \cam\ output and the color-card
output.

To initialize \cam\ for display, the \symdex{PCA} and \symdex{PRA} must
be loaded with the address of the nybble at the lower-right corner of
the screen.  For example, if the upper-left corner of the screen is row
0, column 0, then the lower-right corner will be row {\hex FF}, column
{\hex 3F}.  This will change after a step (see below).

The \symdex{DPYRQ} bit is then set in the \symdex{CCR} to initiate \cam\
display at the end of the current frame.  \symdex{DPYRQ} may be set at
any time, and will become effective at the next beginning-of-frame.
When not stepping, it may be cleared at any time without affecting the
integrity of \cam\ data in the bit-planes.  However, if \symdex{DPYRQ} is
cleared while in the middle of a frame, the Plane Address Registers will
be left in a random state and should be reloaded before further display
or stepping is done.  It is therefore suggested that {\sym DPYRQ} be
cleared only when {\sym VRUN} is zero.

Once \symdex{DPYRQ} is set, it remains in effect until explicitly
cleared.  The \symdex{PRA} and \symdex{PCA} automatically count around
to their original values, so no further program interaction is necessary
to produce a static display.

Because \symdex{PRA} and \symdex{PCA} are used by the
hardware to address the planes during display, no reading or writing
to the planes can be done during display.  References to the tables or
color map are permissible, although doing this during display may
cause incorrect colors to appear for the duration of the reference.
References to the planes may be done during the vertical retrace
interval, but {\sym PRA} and {\sym PCA} should be returned to their
correct values before the next frame begins.

By setting the \symdex{USETAB} bit in the \symdex{CCR}, lookup table
output bits \symdex{TAD1}, \symdex{TAD3}, \symdex{TBD1}, and \symdex{TBD3}
are used instead of the planes' outputs as addresses to the color map.

\section{Stepping}\index{stepping}

To carry out one step of updating, set up the tables as desired
(see Chapter \ref{TableOperation}), set up to display (see above), and
then write to the \symdex{SRQ} with a 1 in bit 7.  A step
will begin at the next beginning-of-frame;  the \symdex{SRQ}
is automatically cleared at the end of the frame.  If the software
reissues a step request at this time, computing can proceed at 60
steps per second; if the software issues the request too late, it
will be deferred until the next frame.

When stepping is in progress, both \symdex{VRUN} and \symdex{PROC} will
be on in the \symdex{SSR}.  If \symdex{INTENB} is set in the
\symdex{CCR}, then an interrupt condition will be raised at the end of
the step, signaling the software to update the relevant registers.  The
interrupt condition can be cleared by clearing \symdex{INTENB}.

After a step has occurred, the data in the planes will be displaced
one byte to the right and one scan line down.  The \symdex{PRA}
and \symdex{PCA} are automatically adjusted to
compensate for this, so the software need take no action to achieve a
stable display.  However, if the planes will be read or written after
a step, the software must keep track of this displacement.  When
addressing the updated planes, 2 must be added to the column address
and 1 to the row address for each step executed.  Similarly, when
reloading the registers with the display origin prior to issuing a
display request, the new origin will have shifted 2 nybbles right and
one scan line down.

Once a step request is recognized, it is automatically canceled at the
end of the frame.  If no further action is taken, \cam\ returns to
\usedex{display mode}.  Thus, single-stepping is the default, and continuous
running is done only by regular requests by the software.

No referencing of the planes or tables should be done while stepping.
The color map may be written at any time, although doing this during
display will cause a color glitch for the duration of the reference
(about 4 pixels of scan).  References to the tables and planes can be
done during the vertical retrace interval without loss of data.


\chapter{Table operation}\label{TableOperation}\index{lookup table}

Each of the two lookup tables comprise 4K entries of 4 bits each.
They occupy addresses {\hex DFC00}--{\hex DFCFF}, with Table
A data in the low-order four bits of each byte and Table B data in the
high-order four bits.  The tables may be addressed by various sources
which are selected by the \symdex{TAA} and \symdex{TBA}
registers.

In normal usage the tables are used to provide the new values for the
bit-planes during a step.  By setting the \symdex{USETAB} bit in
the \symdex{CCR}, table data bits \symdex{TAD1}, \symdex{TAD3},
\symdex{TBD1}, and \symdex{TBD3} may be used in
place of the bit-planes to drive the color map .

\section{Reading and writing the tables}\index{lookup table/io{I/O}}

The tables may be written at any time \cam\ is not stepping, without
danger of destroying data in the bit-planes.  To read or write the
tables, the address source must first be set to use the \pc\ address
bus; this is done by writing zero to both the \symdex{TAA} and the
\symdex{TBA} registers, and setting the \symdex{LDTBL} bit in the
\symdex{CCR}.  The low-order eight bits of address come from the \pc, and
the high-order four bits come from the \usedex{phase bits} ({\sym
P0}--{\sym P3}) in the {\sym AAR}.  Both tables are written or read
simultaneously.

\section{Address sources for the tables}

There are four kinds of address sources available for the tables:

\begin{enumerate}
        \item The \pc\ address bus and \usedex{phase bits}, for loading the tables.
        \item The outputs of the bit-planes.
        \item User connector\index{user connector} pins {\sym UA02}--{\sym UA11} and
{\sym UB02}--{\sym UB11}.
        \item The spatial parity bits, \symdex{H0}, \symdex{H1}, \symdex{V0}, and \symdex{V1}.
\end{enumerate}

The sources selected depend on the setting of {\sym TAS0}--{\sym TAS5} in the
\symdex{TAA} register and {\sym TBS0}--{\sym TBS5} in the \symdex{TBA}
register.  The use of these bits is illustrated in
Tables \ref{TAS} through \ref{TBSM}.

The horizontal parity bit {\sym H0} switches state on each cell, and
its phase can be set by the \symdex{HC0} bit in the {\sym AAR}.
The horizontal parity bit {\sym H1} switches state on every second
cell, and is initially zero at the beginning of a scan line.  The
vertical parity bit {\sym V0} switches on each scan line, and its phase
can be set by the \symdex{VC0} bit in the {\sym AAR}.  The
vertical parity bit {\sym V1} switches on every second scan line, and
is initially zero at the beginning of a frame.

These bits are also used in the \usedex{Margolus neighborhood}, which
is selected by setting bit \symdex{TAM} in the \symdex{TAA}
register and \symdex{TBM} in the \symdex{TBA}
register.  The Margolus neighborhood  affects only table address
bits 2 through 7.  See Tables \ref{TASM} and \ref{TBSM}.

\section{Table Outputs}\index{lookup table}

In normal operation, the \symdex{PCLA} and \symdex{PCLB} bits in the
\symdex{AAR} are both zero and a step results in the planes
getting their new data from the table data bits as shown in Table
\ref{PCLA off}.  Turning on \symdex{PCLA} or \symdex{PCLB} has the
effect shown in Tables \ref{PCLA on} and \ref{PCLB on}.

With \symdex{PCLA} on, external input \symdex{USERA} can be used as if
it were \symdex{PCLA} to switch the plane sources.  With \symdex{PCLB}
on, external input \symdex{USERB} can be used as if it were
\symdex{PCLB} to switch the plane sources.  \symdex{USERA} and
\symdex{USERB} are normally pulled to +5V (i.e., disabled).

\section{External tables}\index{lookup table/external}

The user may connect external logic to replace the function of the
tables.  The connections are made to {\sym UI0}--{\sym UI3} on the
\usedex{user connector}, and these pins are used to write planes 0--3
respectively.  To select the external table for writing planes 0 and 1,
both the \symdex{TAC1} bit in the \symdex{TAA} register and the
\symdex{PCLA} bit in the \symdex{AAR} must be set.  To connect an
external table to planes 2 and 3, the \symdex{TBC1} bit in the
\symdex{TBA} register and the \symdex{PCLB} bit in the \symdex{AAR} must
be set.

\clearpage

\begin{table}[h]
$$
 \begin{tabular}{|c|c|}\hline
Plane & Table Data \\ \hline \hline
0 & \symdex{TAD0} \\ \hline
1 & \symdex{TAD2} \\ \hline
2 & \symdex{TBD0} \\ \hline
3 & \symdex{TBD2} \\ \hline
 \end{tabular}
$$
\caption{Table-to-plane wiring (\symdex{PCLA} and \symdex{PCLB} off).}\label{PCLA off}
\end{table}

\begin{table}[h]
$$
 \begin{tabular}{|c|c|}\hline
Plane & Table Data \\ \hline \hline
0 & \symdex{TAD1} \\ \hline
1 & \symdex{TAD3} \\ \hline
 \end{tabular}
$$
\caption{Table-to-plane wiring (\symdex{PCLA} on).}\label{PCLA on}
\end{table}

\begin{table}[h]
$$
 \begin{tabular}{|c|c|}\hline
Plane & Table Data \\ \hline \hline
2 & \symdex{TBD1} \\ \hline
3 & \symdex{TBD3} \\ \hline
 \end{tabular}
$$
\caption{Table-to-plane wiring (\symdex{PCLB} on).}\label{PCLB on}
\end{table}



\chapter{Color map operation}\index{color map}

The color map is a 16-entry by 4-bit RAM which translates the bit-plane
outputs to Intensity-Red-Green-Blue format for the \pc's color
\usedex{monitor}.  The map is located at addresses {\hex DFA00}--{\hex
DFA0F}.  Only the low nybble of each byte is used.  The data is stored
in complemented form, with a {\tt 0} indicating that the color is turned on
and a {\tt 1} indicating that the color is off.  The map may be written at
any time and the new color assignment becomes effective immediately.
The bit assignments are shown in Table \ref{map bits}.

\begin{table}[h]
$$
 \begin{tabular}{|c|l|}\hline
Bit & \multicolumn{1}{c|}{Color} \\\hline\hline
0 & {\sc not} Intensity \\ \hline
1 & {\sc not} Red \\ \hline
2 & {\sc not} Green \\ \hline
3 & {\sc not} Blue \\ \hline
 \end{tabular}
$$
\caption{Structure of a color-map entry}\label{map bits}
\end{table}

Normally, the color map's four address lines are driven by the outputs
from the four bit-planes.  However, these lines may be made to be driven
by the lookup tables' outputs \symdex{TAD1}, \symdex{TAD3},
\symdex{TBD1}, and \symdex{TBD3}---by setting the \symdex{USETAB} bit in
the \symdex{CCR}.  One use of this feature is to preview the result of a
step without actually changing the contents of the bit-planes.

\chapter{The event counter}\index{event counter}

After a step is computed, a 16-bit count of the number of intensity bits
seen during the step is available at addresses {\hex
DFA00}--{\hex DFA01}.  The \symdex{EVENT} bit in the \symdex{SSR}
indicates the presence of a non-zero count, and therefore distinguishes
between a zero count and a count of 65536.  The count remains valid
until the beginning of the following active step.

Note that the event counter occupies the same addresses as the first
two bytes of the color map.

To use the counter, the color map must be programmed to map
the desired cell events to a color for which the intensity bit is on.
When a step is executed, these events are counted, and this
count becomes available at the end of the frame, when it can be read
by an interrupt service routine.

\chapter{Diagnostics}\label{ChapterDiag}\index{diagnostic}

Three diagnostic signals are available to the software:
\begin{enumerate}
\item
The terminal-count signal from the Plane Row Address
counter (\symdex{PRA}).
\item
The terminal-count signal from the Plane Column
Address counter (\symdex{PCA}).
\item
The terminal-count signal from the color-map output buffer.
\end{enumerate}

Each signal is detected by setting \symdex{P0} and \symdex{P1}
to select the desired signal and reading it back in the
{\sym DIAG} bit in the {\sym SSR}.  The bit settings are shown in Table
\ref{diag select}.

\begin{table}[h]
$$
 \begin{tabular}{|c|c|c|p{2.5in}|}\hline
{\symdex P1} & {\symdex P0} & Signal & Meaning \\ \hline \hline
0 & 0 & \symdex{CMAPTC} & color map output buffer \\ \hline
0 & 1 & \symdex{NCOLTC} & \symdex{PCA} terminal count (active low) \\ \hline
1 & 0 & \symdex{NROWTC} & \symdex{PRA} terminal count (active low) \\ \hline
1 & 1 & \multicolumn{2}{c|}{not defined} \\ \hline
 \end{tabular}
$$
\caption{Diagnostic read-back select.}\label{diag select}
\end{table}

These signals are useful to detect ``stuck'' bits in the three registers,
and to test for proper counter operation.

The color-map output buffer's terminal count is on whenever the
\usedex{monitor} is displaying bright white, i.e., whenever the color
selected has the Red, Green, Blue, and Intensity outputs all on.  By
writing all zeros to the color map, \symdex{CMAPTC} should be on
whenever \symdex{HRUN}, \symdex{VRUN}, and \symdex{DPYLINE} are all on,
indicating that the monitor is displaying.

The \symdex{NCOLTC} signal is low whenever the \symdex{PCA}
contains {\hex FFFF} and the display is not at the
end of a scan line.  Its counting operation can be checked by writing
a number to the \symdex{PCA}, reading or writing an
appropriate number of times to the bit planes, and observing whether
the terminal count signal is generated when the \symdex{PCA}
contents auto-increment to {\hex FFFF}.

The \symdex{NROWTC} signal goes low whenever the \symdex{PRA} contains
{\hex FFFF}, and when the \symdex{PRA} contains 0 and the last line of the
display is being scanned.  The latter function can be checked by writing
1 to the \symdex{PRA}, running the display (the last line of the display
will be line 0), and counting transitions of \symdex{HRUN} in the
\symdex{SSR} to determine when the 256-th line of the display is being
scanned.  {\sym NROWTC} should be off during this period, as well as
during the previous scan line (since the \symdex{PRA} contained {\hex
FFFF} at that time).


\chapter{The user connector}\label{UserConnector}\index{user connector}

A connector is provided for wiring custom neighborhoods 
(by means of jumpers), and complementing or replacing some of
\cam's resources by external circuitry.

\section{Clock}

\symdex{CKBU} is the primary timing reference in the \cam\
system.  All events are synchronized to the rising edge of this clock.

\section{Plane outputs}\index{plane}

The center cell and its eight neighbors are available from each of the
four planes.  These are:
\begin{itemize}
\item \symdex{C0}, \symdex{NW0}, \symdex{N0}, \symdex{NE0}, \symdex{W0}, \symdex{E0}, \symdex{SW0}, \symdex{S0}, \symdex{SE0}
\item \symdex{C1}, \symdex{NW1}, \symdex{N1}, \symdex{NE1}, \symdex{W1}, \symdex{E1}, \symdex{SW1}, \symdex{S1}, \symdex{SE1}
\item \symdex{C2}, \symdex{NW2}, \symdex{N2}, \symdex{NE2}, \symdex{W2}, \symdex{E2}, \symdex{SW2}, \symdex{S2}, \symdex{SE2}
\item \symdex{C3}, \symdex{NW3}, \symdex{N3}, \symdex{NE3}, \symdex{W3}, \symdex{E3}, \symdex{SW3}, \symdex{S3}, \symdex{SE3}
\end{itemize}

\section{Status signals}\index{status}

The following status signals are available: \begin{description}
 \item[\symdex{H00} (active low):] {\sym H00} indicates that the first
pixel of a scan line is being displayed. 
 \item[\symdex{HFF} (active low):] {\sym HFF} indicates that the last
pixel of a scan line is being displayed. 
 \item[\symdex{V00} (active low):] {\sym V00} indicates that the first
scan line of a frame is being displayed. 
 \item[\symdex{VFF} (active low):] {\sym VFF} indicates that
the last scan line of a frame is being displayed. 
 \item[\symdex{HSEL} (active high) and \symdex{VSEL} (active low):] When
asserted, the planes are being updated using edge-neighbors from the
horizontally or vertically adjacent planes (``glued''
edges)\index{glue}.  When not asserted, edge-neighbors are obtained from
the planes themselves, by wrap-araound.
 \item[\symdex{ICAM} (active high):] {\sym
ICAM} is the intensity bit going to the video output connector.  It is
the signal that sets the \usedex{event detector} flip-flop and can be
used to detect events of interest during stepping.
 \item[\symdex{HRUN} (active high):] {\sym HRUN} indicates that the
monitor is in the active part of a scan line.  It can be read as bit 4
in the \symdex{SSR}.  \item[\symdex{VRUN} (active high):] {\sym VRUN}
indicates that the monitor is in the vertically active part of the
screen.  It can be read as bit 5 in the \symdex{SSR}.
 \item[\symdex{PROC} (active high):] {\sym PROC} indicates that a step
is being performed.  It can be read as bit 7 in the \symdex{SSR}.
 \item[\symdex{HT} and \symdex{VT}:] {\sym HT} and {\sym VT}
are the the horizontal and vertical spatial parity bits {\sym H0} and
{\sym V0}, after optional inversion by {\sym HC0} and {\sym VC0} in the
\symdex{AAR}.
 \item[The Phase Bits {\sym P0}--{\sym P3}:]\index{phase bits} These are settable from
the \symdex{AAR}.
 \end{description}

\section{Control bits}

With the \symdex{PCLA} bit in the \symdex{AAR} set, external input
\symdex{USERA} can be used as if it were \symdex{PCLA} to switch the
plane sources.  With \symdex{PCLB} on, external input \symdex{USERB} can
be used as if it were \symdex{PCLB} to switch the plane sources.
\symdex{USERA} and \symdex{USERB} are normally pulled to +5V (i.e.,
disabled).

\section{Plane inputs}\index{plane}

When \symdex{PCLA} in the \symdex{AAR} and \symdex{TAC1} in the
\symdex{TAA} register are both on, \symdex{UI0} and \symdex{UI1} are
selected as input sources to planes 0 and 1, respectively.  When
\symdex{PCLB} in the \symdex{AAR} and \symdex{TBC1} in the \symdex{TBA}
register are both on, \symdex{UI2} and \symdex{UI3} are selected as
input sources to planes 2 and 3, respectively.

\section{Table address inputs}\index{lookup table}

Table A addresses may be provided by user address bits {\sym UA02}--{\sym UA11}.
{\sym UB02}--{\sym UB11} can provide Table B addresses.

\section{Spare pins}

Four pins are provided on the user connector for hardware patches and
future enhancements.

\chapter{Multiple CAMs}\label{multiCAM}\index{multiple cams{multiple {\sc cam}s}}

Up to eight \cam\ boards may be cabled together within a system, with
one acting as master and the others as slaves.  With additional
hardware to buffer the timing and control logic, up to 64 cards may be
used in a system. (Of course, the \pc\ contains neither the slots
nor the power for this many cards, so a special backplane is required
for such large systems).  The master provides all clocks and
synchronization signals, while those on the slave cards are disabled.
The \usedex{monitor} can only show the output of the card to
which it is physically connected.  By daisy-chaining the video-out of
one card to the video-in of another, the software can be given control
over which card is used to generate the display.

\section{Connecting CAMs together}

Without modification, a \cam\ card operates as a master occupying
addresses from {\hex DF800} to {\hex DFFFF} hex.  When a second card is added to a
system, the Master-Out connector ({\sym J16}) on one card (designated
the master) is connected to the Slave-In connector ({\sym J15}) on the
slave card via a 16-conductor ribbon cable.  The cable connects all
pins from the master's connector to the slave's connector; by this cabling, the
address of the first slave is automatically changed as shown in Table \ref{slave
addresses}.

When additional slaves are connected (up to a maximum of seven
slaves), the Slave-Out connector ({\sym J14}) of each slave card is
connected to the Slave-In connector ({\sym J15}) of the next slave by a
cable.

The master-slave cable and most of the slave-slave cables are wired in a
straightforward manner, so as to connect corresponding pins of the sixteen-pin
connectors on each end (i.e., pin 1 to pin 1, pin 2 to pin 2, etc.; this effect
is obtained automatically when clamping a 16-pin female header onto each end
of a 16-wire flat cable). However, a modified wiring is necessary on two
of the slave-slave cables, namely that between slaves 3 and 4 and that
between slaves 4 and 5. For these cables only, pin 16 on the Slave-Out
end is wired to pin 14 on the Slave-In end, while pins 14 on the Slave-Out end
and pin 16 on the Slave-In end are left unconnected. This can conveniently be done
by making a straight-wired cable as described above, then cutting and
custom-reconnecting wires 14 and 16 in the cable. When this is done, one end of
the cable should be distinctively marked (e.g., ``Slave-Out, \cam\ 3 or 4''), as
the modified cable is no longer end-to-end symmetric.

\begin{table}[h]
$$
 \begin{tabular}{|c|r@{--}l|}\hline
CAM card & \multicolumn{2}{c|}{Address Range} \\ \hline \hline
Master & \hex DF800 & \hex DFFFF \\ \hline
1st Slave & \hex DF000 & \hex DF7FF \\ \hline
2nd Slave & \hex DE800 & \hex DEFFF \\ \hline
3rd Slave & \hex DE000 & \hex DE7FF \\ \hline
4th Slave & \hex DD800 & \hex DDFFF \\ \hline
5th Slave & \hex DD000 & \hex DD7FF \\ \hline
6th Slave & \hex DC800 & \hex DCFFF \\ \hline
7th Slave & \hex DC000 & \hex DC7FF \\ \hline
 \end{tabular}
$$
\caption{Address select settings}\label{slave addresses}
\end{table}

\section{Master-slave connections}

Those signals with suffix \symdex{LOC} on the master card must be tied
to the corresponding signals with suffix \symdex{EXT} on the slave
cards.  These are
\locextdex{CLK0B},
\locextdex{CLK0A},
\locextdex{PROC},
\locextdex{DPYLINE},
\locextdex{HPE}, and
\locextdex{VPE}.
These signals are automatically connected in the correct fashion when
cables are used as described above.

\chapter{Gluing planes together}\label{ChapterGlue}\index{glue}

An unmodified \cam\ has four bit-planes of size 256\by256.  Since some
experiments will require larger arrays, a provision is made for
``gluing'' the edges of planes from one or more cards together.  Each
card is provided with a vertical glue connector and a horizontal glue
connector.  Each connector contains an ``in'' pin and an ``out'' pin for
each plane, plus their associated grounds to limit electrical noise, for
a total of 16 pins per connector.  By cross-connecting the in and
out pins of two planes on either their horizontal or vertical edges (or
both) and setting the appropriate glue bit(s) in the \symdex{CCR}, the
two planes become one large plane.

For example, suppose one desires to glue plane 0 to plane 2.  One would
connect signal {\sym VSE0IN} to {\sym VSE2OUT}, {\sym VSE2IN} to {\sym
VSE0OUT}, {\sym HSE0IN} to {\sym HSE2OUT}, and {\sym HSE2IN} to {\sym
HSE0OUT}.  Additionally, since gluing is turned off and on {\sl for all
four planes} simultaneously, the non-glued planes should be connected to
themselves (explicitly gluing a plane to itself by means of a cable and
a glue bit gives the same result as the default internal connection).
If this additional glueing is not done, unpredictable data (typically
{\tt 1}'s) will be fed to the edges of the unglued planes.

With the planes wired, the \symdex{HGLUE} and \symdex{VGLUE} bits in the
\symdex{CCR} are set; planes 0 and 2 then behave as a single periodic structure
with a period of 512 sites in either direction, as illustrated below; note that this is not
the same as a 512\by512 array with toroidal wrap-around.
 $$
 \begin{tabular}{c|c|c|c|c}
$\cdots$ & $\cdots$ & $\cdots$ & $\cdots$ & $\cdots$ \\\hline
$\cdots$ & plane 0 & plane 2 & plane 0 & $\cdots$\\\hline
$\cdots$ & plane 2 & plane 0 & plane 2 & $\cdots$\\\hline
$\cdots$ & plane 0 & plane 2 & plane 0 & $\cdots$\\\hline
$\cdots$ & $\cdots$ & $\cdots$ & $\cdots$ & $\cdots$
 \end{tabular}
 $$
 \noindent Gluing is permitted from one card to another, but not from one kind
of edge to another (i.e., from a horizontal edge to a vertical edge).

In addition to gluing cables, some extra multiplexing circuitry is
necessary to create sheets greater than 512\by512, as described in a
separate application note.

\chapter{Address and interrupt conflicts}\label{address conflict}

If one wants to use on the \pc\ bus some other card whose address range
conflicts with \cam's normal address range, \cam\ can be moved to lower
addresses, in 16K-byte increments; this is particularly important when
using more than eight \cam{}s.  This modification involves the
installation of from one to three jumpers (see Table \ref{address
jumper}).  The default case is no jumpers installed.\index{address conflict}

\begin{table}[h]
$$
 \begin{tabular}{|c|c|}\hline
Jumper & Address Shift (Bytes) \\ \hline \hline
{\sym J11-1} to {\sym J11-2} & $-$16K \\ \hline
{\sym J11-3} to {\sym J11-4} & $-$32K \\ \hline
{\sym J11-5} to {\sym J11-6} & $-$64K \\ \hline
 \end{tabular}
$$
\caption{Effect of address jumpers}\label{address jumper}
\end{table}

Similarly, if other hardware uses {\sym IRQ2} for its interrupt, \cam\ can be
configured to interrupt on {\sym IRQ3} or {\sym IRQ4} instead, using the
jumper at {\sym J10}.  Table \ref{IRQ jumper} shows the correspondence
between the pins jumpered and the IRQ that \cam\ interrupts on.\index{interrupts}

\begin{table}[h]
 $$
  \begin{tabular}{|c|c|}\hline
Jumper & Interrupt \\ \hline \hline
\sym J10-1 to \sym J10-2 & \sym IRQ2 \\ \hline
\sym J10-3 to \sym J10-4 & \sym IRQ4 \\ \hline
\sym J10-5 to \sym J10-6 & \sym IRQ3 \\ \hline
  \end{tabular}
 $$
 \caption{Effect of {\sym IRQ} Jumper}
 \label{IRQ jumper}
\end{table}

\cleardoublepage

\begin{theindex}
\addcontentsline{toc}{chapter}{Index}
\input index
\end{theindex}

\end{document}
