6.915 Digital Systems Engineering

how to make computers go real fast, reliably.

Summary

Logistics

Schedule

Lecture Notes

Assignments

Readings


Summary

The speed, reliability, and power dissipation of a digital system are largely determined by the system-level electrical issues. This course addresses the most important of these issues including:
Signalling Conventions
To transport a bit, it is encoded as a current or a voltage on a wire. A good encoding method or signalling convention allows high bit rates (gigabits/s) at low power by isolating signals from noise. Most conventional signalling conventions, such as those implemented by most off-the-shelf TTL and CMOS parts, on the other are limited to 100Mb/s or less and consume large amounts of power. We will discuss the fundamentals of signalling with examples drawn from a number of high-performance signalling conventions.

Timing and Synchronization
A timing convention governs when symbols are placed on wires and when they are sampled off. Most digital systems today use synchronous timing conventions that present challenging problems in clock distribution. Passing information between parts of a system that employ different timing conventions requires synchronization. In some cases, a system may operate completely asynchronously. Very often, the choice of timing conventions and synchronization methods makes a very large difference in the speed and reliability of a system. In particular we will see that, with the proper choice of timing convention, the throughput of a system is limited only by the timing noise (skew and jitter), not by delay. We will discuss the fundamentals of timing and synchronization and look at examples of succesful and unsuccessful approaches to timing.

Noise in Digital Systems
Noise is the dominant concern in the design of both signalling and timing conventions. The dominant noise sources in digital systems, such as power supply noise, crosstalk, and inter-symbol interference, are actually interference generated by the system itself. Other sources, such as thermal noise and alpha particles are truly noise. In either case, understanding noise and managing it is essential to the reliable high-speed operation of a digital system. We will survey the most important sources of noise in a digital system and present a methodology of budgeting for noise, both amplitude and timing noise.

Power Distribution
Digital systems demand large amounts of AC current (kA are not unusual) while requiring a stable DC voltage (to within a few hundred mV). The current may switch from zero to peak and back to zero in a few ns giving peak derivatives of 10^12 A/s or more. Off-chip bypass capacitors, which look more like inductors over 20MHz, are of little help in smoothing this current demand. We will examine this problem in detail and look at a number of approaches for solving it.


Logistics

Instructor
Professor William J. Dally
Teaching Assistant
To Be Determined
Time
Tuesday and Thursday 11:00 to 12:30
Location
36-144
Text
Digital Systems Engineering
William J. Dally and John Poulton
(Draft chapters of this book will be handed out as course notes)
Prerequisite
6.002 Required, 6.004 Recommended

Grading
Two quizes (50%)
Problem sets (20%)
Class project (20%)
Participation (10%)


Schedule

No Date Topic Out In
1 5 Sept Introduction: What is digital systems engineering. The problems of noise, signalling, timing, and synchronization. Outline of the course. A brief diagnostic test will be given.
2 10 Sept Building Blocks: Packaging of digital systems. Electrical properties of wires. Transmission lines.
3 12 Sept Lumped and distributed models of wires. Lossy and lossless lines. Demonstration of TDR/TDT. PS1
4 17 Sept Transmission line wrapup and review. Buses. Examples. Question and answer.
5 19 Sept Noise: Noise sources in digital systems. Proportional and fixed noise. Bounded and gaussian noise. Noise budgets. Power supply noise. Parameter mismatch. PS2 PS1
6 24 Sept Crosstalk: Crosstalk to capacitive lines, crosstalk between LC transmission lines, signal return crosstalk.
7 26 Sept Inter-symbol interference. Stochastic noise sources. Some example noise budgets. PS3 PS2
8 1 Oct Signalling: The signalling problem. Impedance, levels, terminations, and references. What's wrong with most signalling methods.
9 3 Oct Signalling over transmission lines. Current-mode signalling. Voltage-mode signalling. Source- and under-terminated signalling. Unipolar vs. bipolar signalling. PS4 PS3
10 8 Oct References: what are references, isolating supply noise from references, differential and pseudo-differential signalling.
11 10 Oct Signalling over lumped media, low-voltage signalling, SRAM example, pulsed signalling. Dealing with lead inductance, rise-time control and current shaping. PS5 PS4
15 Oct Columbus Day Holiday - No Class
12 17 Oct Signalling over lossy lines: on-chip RC lines. Typical response, repeaters, overdriving. Review for Quiz 1. PS5
13 22 Oct QUIZ 1: Wires, Noise, and Signalling
14 24 Oct Timing: Introduction to system timing. Timing nomenclature. Encoding events. Examples of timing conventions.
15 29 Oct Synchronus and pipeline timing.
16 31 Oct Closed-loop timing. Phase-lock and delay-lock loops. Per-signal deskew. PS6
17 5 Nov Clock distribution: the distribution problem. Off-chip distribution, balanced clock trees, salphasic clocking, synchronized oscillators. On-chip distribution, clock trees and grids.
18 7 Nov Synchronization: The synchronization problem: deciding which event came first. Metastability and synchronization failure. Calculation of failure probability. Basic synchronizer design. PS7 PS6
19 12 Nov Synchronizers for Periodic Signals: The synchronization heirarchy. FIFO and dual-register synchronizers. Flow-control. Clock prediction.
20 14 Nov Introduction to asynchronous design. The clock stopper. Trajector maps. Asynchronous protocols and the weak conditions. Composing asynchronous circuits. Asynchronous pipelines and state machines. PROJ PS7
21 19 Nov Power Distribution The power distribution problem. Off-chip distribution. LC Sections. Shunt regulators and clamps. Switching converters. Bypass capacitors and their inductance.
22 21 Nov On-chip power distribution. IR drops. Symbiotic bypass capacitance. Typical current profiles. On-chip regulators.
23 26 Nov QUIZ 2: Timing, Synchronization, and Power Distribution
28 Nov Thanksgiving Holiday - No Class.
24 3 Dec Project presentations
25 5 Dec Project presentations PROJ
26 10 Dec Course overview, (cookies and refreshments served)

Lecture Notes


Last updated 9/4/96 by William J. Dally (billd@ai.mit.edu)