No | Date | Topic | Out | In |
---|---|---|---|---|
1 | 5 Sept | Introduction: What is digital systems engineering. The problems of noise, signalling, timing, and synchronization. Outline of the course. A brief diagnostic test will be given. | ||
2 | 10 Sept | Building Blocks: Packaging of digital systems. Electrical properties of wires. Transmission lines. | ||
3 | 12 Sept | Lumped and distributed models of wires. Lossy and lossless lines. Demonstration of TDR/TDT. | PS1 | |
4 | 17 Sept | Transmission line wrapup and review. Buses. Examples. Question and answer. | ||
5 | 19 Sept | Noise: Noise sources in digital systems. Proportional and fixed noise. Bounded and gaussian noise. Noise budgets. Power supply noise. Parameter mismatch. | PS2 | PS1 |
6 | 24 Sept | Crosstalk: Crosstalk to capacitive lines, crosstalk between LC transmission lines, signal return crosstalk. | ||
7 | 26 Sept | Inter-symbol interference. Stochastic noise sources. Some example noise budgets. | PS3 | PS2 |
8 | 1 Oct | Signalling: The signalling problem. Impedance, levels, terminations, and references. What's wrong with most signalling methods. | ||
9 | 3 Oct | Signalling over transmission lines. Current-mode signalling. Voltage-mode signalling. Source- and under-terminated signalling. Unipolar vs. bipolar signalling. | PS4 | PS3 |
10 | 8 Oct | References: what are references, isolating supply noise from references, differential and pseudo-differential signalling. | ||
11 | 10 Oct | Signalling over lumped media, low-voltage signalling, SRAM example, pulsed signalling. Dealing with lead inductance, rise-time control and current shaping. | PS5 | PS4 |
15 Oct | Columbus Day Holiday - No Class | |||
12 | 17 Oct | Signalling over lossy lines: on-chip RC lines. Typical response, repeaters, overdriving. Review for Quiz 1. | PS5 | |
13 | 22 Oct | QUIZ 1: Wires, Noise, and Signalling | ||
14 | 24 Oct | Timing: Introduction to system timing. Timing nomenclature. Encoding events. Examples of timing conventions. | ||
15 | 29 Oct | Synchronus and pipeline timing. | ||
16 | 31 Oct | Closed-loop timing. Phase-lock and delay-lock loops. Per-signal deskew. | PS6 | |
17 | 5 Nov | Clock distribution: the distribution problem. Off-chip distribution, balanced clock trees, salphasic clocking, synchronized oscillators. On-chip distribution, clock trees and grids. | ||
18 | 7 Nov | Synchronization: The synchronization problem: deciding which event came first. Metastability and synchronization failure. Calculation of failure probability. Basic synchronizer design. | PS7 | PS6 |
19 | 12 Nov | Synchronizers for Periodic Signals: The synchronization heirarchy. FIFO and dual-register synchronizers. Flow-control. Clock prediction. | ||
20 | 14 Nov | Introduction to asynchronous design. The clock stopper. Trajector maps. Asynchronous protocols and the weak conditions. Composing asynchronous circuits. Asynchronous pipelines and state machines. | PROJ | PS7 |
21 | 19 Nov | Power Distribution The power distribution problem. Off-chip distribution. LC Sections. Shunt regulators and clamps. Switching converters. Bypass capacitors and their inductance. | ||
22 | 21 Nov | On-chip power distribution. IR drops. Symbiotic bypass capacitance. Typical current profiles. On-chip regulators. | ||
23 | 26 Nov | QUIZ 2: Timing, Synchronization, and Power Distribution | ||
28 Nov | Thanksgiving Holiday - No Class. | |||
24 | 3 Dec | Project presentations | ||
25 | 5 Dec | Project presentations | PROJ | |
26 | 10 Dec | Course overview, (cookies and refreshments served) |